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Patent Searching and Data


Title:
FABRICATION OF MASK ROM
Document Type and Number:
Japanese Patent JPH0722523
Kind Code:
A
Abstract:

PURPOSE: To rationalize a fabrication process by achieving the formation of a protective film just after ion implantation by etching a layer insulating film taking an Al wiring as a mask and selectively implanting impurity into a channel region of a memory cell transistor.

CONSTITUTION: On the surface of a semiconductor substrate 11 bit lines B are formed and further word lines WL, a silicon nitrided film SN, and a layer insulating film 12 with a reduced pressure CVD process. An Al wiring 13 is formed by sputtering and patterning Al over the entire surface of the substrate. The layer insulating film 12 is etched with use of the Al wiring 13 as a mask and a channel region CH of a memory cell transistor MT is rendered to selective ion implantation. A protective film 14 is formed so as to cover the semiconductor substrate 11. The layer insulating film 12 is etched using the Al wiring 13 as a mask in such a manner whereby a region where the layer insulating film 12 is removed is widened and hence no 'cavity' is produced even when the protective film 14 is formed at once.


Inventors:
TAKAO YUKIHIRO
Application Number:
JP15711893A
Publication Date:
January 24, 1995
Filing Date:
June 28, 1993
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H01L27/112; H01L21/8246; (IPC1-7): H01L21/8246; H01L27/112
Attorney, Agent or Firm:
Takuji Nishino