Title:
同期型周波数分周器およびその構成要素
Document Type and Number:
Japanese Patent JP2007515821
Kind Code:
A
Abstract:
The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry ( 76 ) for the least significant bit receiving at its Carry-input a "1", and each further latch circuity receiving at its Carry-input the carry signal from the latch circuitry of the previous digit, and an And gate circuitry receiving the Sum outputs of the latch circuitries.
Inventors:
Muller, Bald
Application Number:
JP2005508355A
Publication Date:
June 14, 2007
Filing Date:
August 28, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K23/64; H03K3/2885; H03K23/50; H03K23/66
Attorney, Agent or Firm:
Tadahiko Ito