Title:
ロック検出器、ロックアルゴリズム、拡張された範囲のVCOおよび簡単化された二重モジュラス除算器を備えたシンセサイザ
Document Type and Number:
Japanese Patent JP2004531107
Kind Code:
A
Abstract:
The present invention provides a synthesiser having a divide circuit implemented using only a single counter along with a decoder. This allows for a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
Inventors:
Sue, David Kay
You, Chik Patrick
Weber, David Jay
Zagari Ma Sound
You, Chik Patrick
Weber, David Jay
Zagari Ma Sound
Application Number:
JP2002553309A
Publication Date:
October 07, 2004
Filing Date:
December 17, 2001
Export Citation:
Assignee:
Atheros Communications, Inc.
International Classes:
H03K23/66; H03L7/095; H03L7/099; H03L7/10; H03L7/183; H03L7/193; H03L7/089; (IPC1-7): H03L7/095; H03L7/099; H03L7/10; H03L7/183
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto