Title:
カウンタをインプリメントするシステムおよび方法
Document Type and Number:
Japanese Patent JP4303528
Kind Code:
B2
Abstract:
A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of the counter are grouped into a binary portion of the counter of m bits and a unary portion of the counter of n bits. In order to increment the counter, the unary portion of the counter is incremented first. When the unary portion of the counter reaches a specific value, the binary portion of the counter is incremented. This limits 1 to 0 bit transitions and allows a large range of unique values to be read from the counter. In another embodiment, two unary counters are formed, which dynamically change in size as the counter is incremented.
Inventors:
Paul england
Marcus Paynard
Marcus Paynard
Application Number:
JP2003181886A
Publication Date:
July 29, 2009
Filing Date:
June 25, 2003
Export Citation:
Assignee:
MICROSOFT CORPORATION
International Classes:
G06F12/16; G11C16/10; G11C16/34; H03K21/00; H03K21/40
Domestic Patent References:
| JP63094716A | ||||
| JP3091852A |
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Kazuo Abe