Title:
A system and a method of maintaining the input impedance of a current mode circuit
Document Type and Number:
Japanese Patent JP5912983
Kind Code:
B2
Abstract:
In accordance with some embodiments of the present disclosure, a circuit comprises an input node configured to receive a current-mode input signal and an input stage that includes an input device communicatively coupled to the input node. The input device is configured to receive the input signal at the input node. The circuit additionally comprises bias circuitry communicatively coupled to the input stage and configured to provide a bias current for the input device. The bias circuitry is also configured to remove at least a portion of the bias current from the input signal through a feedback loop associated with the input node such that the input signal is received by the input device with at least a portion of the bias current removed. The circuit further comprises an output stage communicatively coupled to the input stage and configured to output a current-mode output signal based on the input signal.
Inventors:
Yui Choanujao
Oriaei Omid
Newman David
Gomez Michael El
Oriaei Omid
Newman David
Gomez Michael El
Application Number:
JP2012176154A
Publication Date:
April 27, 2016
Filing Date:
August 08, 2012
Export Citation:
Assignee:
Intel IP Corporation
International Classes:
H04B1/04
Domestic Patent References:
| JP11507773A | ||||
| JP61035004A | ||||
| JP2165709A | ||||
| JP2006060455A | ||||
| JP61005321A |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki