Title:
データ収集システムのノイズを抑制するためのシステム
Document Type and Number:
Japanese Patent JP5020592
Kind Code:
B2
Abstract:
The system includes a number of terminals, at least one of which is coupled to a signal line of a detector element. A circuit board connecting part is arranged adjacent to the detector to reduce the input capacitance of the detector element signal line. At least one connecting part or slot is configured to receive one analog/digital converter board (300). The connecting slot is also able to receive two A/D boards in a back-to-back configuration. The A/D board preferably comprises a number of application-specific integrated circuit (ASIC) chips. An independent claim is included for an imaging system.
Inventors:
Swamina Asan Narasimhan
Koji Bessho
Koji Bessho
Application Number:
JP2006280495A
Publication Date:
September 05, 2012
Filing Date:
October 13, 2006
Export Citation:
Assignee:
GENERAL ELECTRIC COMPANY
International Classes:
G03B42/00; A61B6/03; H04N5/32
Domestic Patent References:
| JP4110691A | ||||
| JP4134290A | ||||
| JP2005128000A | ||||
| JP2005265859A |
Foreign References:
| US6472668 | ||||
| US6867870 | ||||
| US20040264632 |
Attorney, Agent or Firm:
Arakawa Satoshi
Hirokazu Ogura
Toshihisa Kurokawa
Hirokazu Ogura
Toshihisa Kurokawa