Title:
BONDING METHOD OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3042468
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To avoid a release of a pad of a semiconductor chip as well as the breakdown of Si as the major material of the semiconductor chip, by a method wherein the electrode of a semiconductor chip and the bump of a wiring board are junctioned with each other, while the periphery of the electrode and the periphery of the bump are junctioned with each other at the some time.
SOLUTION: An Al electrode pad 11 of a semiconductor chip 1 as well as an inner bump 25 of a TAB tape 21 corresponding to the Al electrode pad 11 are aligned with each other. Next, the Al pad 11 of the semiconductor chip 1 is joined with the inner bump 25, and at the some time a chip cover 12a around Al electrode pad 11 joined with an adhesive tape 23a around the inner bump 25. Through these procedures, the stress of the thermal expansion-cooling contraction of the TAB tape 21 is imposed on the entire junction region C' of a metallic junction region M and adhesive junction region R, so that stresses are dispersed widely in the entire junctioned region C' thereby making the stress per unit area reduced.
Inventors:
Hirofumi Hotta
Application Number:
JP28736397A
Publication Date:
May 15, 2000
Filing Date:
October 20, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)