TEST CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND TEST METHOD USING THE SAME

Japanese Patent JP2016186428

A

PROBLEM TO BE SOLVED: To detect the delay fault in the path from a combination circuit in the last stage of the previous logic circuit to a memory circuit, or the path from the memory circuit to the following combination circuit.SOLUTION: A test circuit is used to detect the delay fault of a semiconductor integrated circuit including an output control circuit including a plurality of sequential circuits, a combination circuit connected following the output control circuit, and a memory circuit connected following the combination circuit, and a combination circuit following the memory circuit. The result of a predetermined process on the output of a first sequential circuit among the plurality of sequential circuits is input to the first sequential circuit. Predetermined data are stored in the memory circuit through the combination circuit in accordance with the result of the predetermined process with a predetermined alteration of the clock. The data are read out from the memory circuit in the next alteration after an odd number of alterations after the predetermined alteration of the predetermined clock. The data and a first state are compared and based on the result of comparison, the delay fault is detected.SELECTED DRAWING: Figure 1

NAKAMURA HIROYUKI

JP2015065953A

October 27, 2016

March 27, 2015

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MEGA CHIPS CORP

G01R31/28; G11C7/00; G11C29/56

JP2009205414A	2009-09-10
JP2006073917A	2006-03-16
JP2001013220A	2001-01-19
JPH1123660A	1999-01-29
JP2001004710A	2001-01-12

US20120198294A1

2012-08-02

Patent Services Corporation m&s Partners
Hideaki Shioya
Akihiko Miyazaki

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