Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
薄膜トランジスタ表示板とその製造方法
Document Type and Number:
Japanese Patent JP5107504
Kind Code:
B2
Abstract:
A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.

Inventors:
Park Uku
All phases
Park Park
Lee
White standard
Willow
Basis
Lee Wan
Choi Yong
Application Number:
JP2004249403A
Publication Date:
December 26, 2012
Filing Date:
August 30, 2004
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G02F1/136; G02F1/1368; G02F1/133; G02F1/1339; G03C1/85; G03C5/00; G09F9/30; H01L21/00; H01L21/336; H01L29/786
Domestic Patent References:
JP2000164886A
JP2002353465A
JP2000066240A
JP2003045893A
JP2004212964A
JP2001230321A
Attorney, Agent or Firm:
Yamashita
Yukio Ono
Tomoko Inazumi