Title:
OPTICAL SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3208307
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the noise of the current flowing to a photodiode having a photodiode and a CMOS (a pair of N-channel and p-channel MOS transistor), and to improve the high speed responsiveness of the photodiode.
SOLUTION: An I-type semiconductor layer 2 is formed on a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is formed on the I-type semiconductor 2. An N+-type buried layer 4 is provided on the region, ranging from the lower part of the P-channel MOS transistor forming region 22, located between the I-type semiconductor layer 2 and the epitaxial layer 3, to the lower part of an N-channel MOS transistor forming region. The current, which flows to a photodiode, is prevented from flowing to a well region 7 by the buried layer 4 and the I-type semiconductor layer 2. Also, a thick depletion layer is formed by the I-type semiconductor layer 2 provided between the substrate 1 and the epitaxial layer 3, and the high speed responsiveness of the photodiode can be improved.
Inventors:
Tsuyoshi Takahashi
Toshiyuki Ohkota
Satoshi Kaneko
Toshiyuki Ohkota
Satoshi Kaneko
Application Number:
JP30763895A
Publication Date:
September 10, 2001
Filing Date:
November 27, 1995
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H01L27/092; H01L21/8238; H01L31/10; (IPC1-7): H01L31/10; H01L21/8238; H01L27/092
Domestic Patent References:
| JP63122267A | ||||
| JP4304665A | ||||
| JP5226627A | ||||
| JP7231076A | ||||
| JP613643A | ||||
| JP1238154A |
Attorney, Agent or Firm:
Masamasa Shibano
Previous Patent: How [to have chopsticks] correcting implement
Next Patent: MANUFACTURE OF SOLID ELECTROLYTIC CAPACITOR
Next Patent: MANUFACTURE OF SOLID ELECTROLYTIC CAPACITOR