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Title:
低減されたジッタを備える改良された分周器及びそれに基づく送信器
Document Type and Number:
Japanese Patent JP4386725
Kind Code:
B2
Abstract:
An apparatus for generating an output signal whose frequency is lower than the frequency of an input signal is disclosed. The apparatus includes a chain of frequency dividing cells where each cell has a definable division ratio. Furthermore, the frequency dividing cells include a clock input for receiving an input clock, a divided clock output for providing an output clock to a subsequent frequency dividing cell, a mode control input for receiving a mode control input signal from the subsequent frequency dividing cell, and a mode control output for providing a mode control output signal to a preceding frequency dividing cell. The apparatus may further includes a logic network having one or more inputs where each input is connected to a mode control input of one of the frequency dividing cells.

Inventors:
Wang Zenhua
Application Number:
JP2003524117A
Publication Date:
December 16, 2009
Filing Date:
August 22, 2002
Export Citation:
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Assignee:
NXP B.V.
International Classes:
H03K23/64; H03K21/10; H03K23/66; H03K23/68; H03L7/197; H04B1/04
Domestic Patent References:
JP3136520A
JP590953A
JP4212522A
JP6244721A
JP5506338A
JP7307664A
JP5448475A
Foreign References:
WO1997006600A1
Other References:
SHPERLING I,SIGMA DELTA MODULATOR WITH A RANDOM OUTPUT BIT STREAM OF SPECIFIED 1/0 AVERAGE RATIO,MOTOROLA TECHNICAL DEVELOPMENTS,1993年 3月 1日,V18,P156-160
Cicero S.Vaucher他,「A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology」,IEEE JOURNAL OF SOLID-STATE CIRCUITS,米国,IEEE,2000年 7月,VOL.35, NO.7,pp1039-1045
柳沢 健編,PLL(位相同期ループ)応用回路,日本,総合電子出版社,1977年 9月20日,第1版,57頁,プログラマブル・カウンタ
Attorney, Agent or Firm:
Kenji Sugimura
Tatsuya Sawada
Akito Okura