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Title:
The trench DMOS device for the high-voltage use provided with the improved termination structure
Document Type and Number:
Japanese Patent JP5990525
Kind Code:
B2
Abstract:
A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.

Inventors:
Ji Wei Su
Florin Udrea
Lee Yin Lin
Application Number:
JP2013535075A
Publication Date:
September 14, 2016
Filing Date:
October 20, 2011
Export Citation:
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Assignee:
VISHAY GENERAL SEMICONDUCTOR,LLC
International Classes:
H01L29/78; H01L21/336; H01L29/06; H01L29/41; H01L29/47; H01L29/872
Domestic Patent References:
JP2002208711A
JP2008533696A
JP2007258742A
JP2002164541A
JP2013522909A
Foreign References:
US20090057756
US20050062124
Attorney, Agent or Firm:
Yasuhiko Murayama
Masatake Shiga
Takashi Watanabe
Shinya Mitsuhiro