PURPOSE: To configure a data processing system whose power consumption is low by a method wherein a memory block whose high-speed access is not requested form a CPU is detected and its refresh operation is performed in a low-power mode.

CONSTITUTION: DRAMs inside units U1 to U3 to which select signals SEL1 to SEL3 have been connected are refresh-driven at low power irrespective of an REF signal, an MR signal and an MW signal. A unit U0 in which a select signal SEL0 is at '1' is selected as a memory bank and controlled by the REF signal, the MR signal and the MW signal. When it is selected as the memory bank, a memory read operation, a memory write operation and a high-speed refresh operation are performed in the same manner as a general memory access operation.