PURPOSE: To shorten a total channel switching time.

CONSTITUTION: When one of DMA request signals 101 corresponding to plural channels becomes active, a DMA transfer start signal 103 is outputted, a bus cycle sequencer block 19 outputs a DMA transfer permission signal 109 corresponding to the DMA request channel, and a transfer frequency block 1 calculates the number of transfer bytes of data stored in a mode register 7. The DMA transfer request signal 101 is encoded and request data are inputted to a comparator 16 together with one of transfer start and interruption state signals 105 and 106; and the contents of a transfer byte storage register 2 and the number of transfer bytes generated by a constant generation block 9 are inputted to a comparator 17 simultaneously, and both the inputs are inputted to an AND circuit 18. When the value of a transfer byte storage register 2 is equal to or less than the value of the constant generation block 9, the comparator 17 generates a '0'-level output, the output of the comparator 16 is masked, and channel switching when the the remaining transfer bytes are small is suppressed.