Title:
Evaluation method for devices containing multiple electrical circuits
Document Type and Number:
Japanese Patent JP6338830
Kind Code:
B2
Abstract:
A method for evaluating a device including a plurality of electric circuits has: a step of finding a first malfunction frequency property for individual electric circuits included in the device, the first malfunction frequency property representing the magnitude of a critical noise signal at which each electric circuit causes a malfunction; and a step of finding a second malfunction frequency property based on the first malfunction frequency property found for each of the electric circuits, an equivalent circuit of the entire device, and an equivalent circuit of each of the electric circuits, the second malfunction frequency property representing the magnitude of a critical noise signal at which the entire device causes a malfunction.
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| JPWO2009066764 | Semiconductor integrated circuit equipment and its test method |
Inventors:
Noriaki Hiraga
Application Number:
JP2013141376A
Publication Date:
June 06, 2018
Filing Date:
July 05, 2013
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
G01R31/30; G01R31/00
Domestic Patent References:
| JP2003216682A | ||||
| JP2007278781A | ||||
| JP3270302A | ||||
| JP2009210322A | ||||
| JP4157558A |
Other References:
市川浩司,櫻井礼彦,稲垣正史,松井武,馬淵雄一,中村篤,林亨,基板解析への応用に向けたLSIイミュニティ評価法の検討,電子情報通信学会技術研究報告.EMJ,環境電磁工学,一般社団法人電子情報通信学会,2004年,77~82頁
Attorney, Agent or Firm:
Sano patent office