Title:
A verification support program and a verification support method
Document Type and Number:
Japanese Patent JP6255982
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve efficiency in verification.SOLUTION: A verification support device 100 acquires, with respect to each of multiple sets, read time Tbased on: each value of multiple first variables corresponding to a non-defective rate shown in non-defective information for each set; and a performance value of a sense amplifier in each set. The verification support device generates a function f (V,σ) on the basis of the respective acquired read time T. The verification support device 100 retrieves, from multiple first combination candidates of each value of multiple second variables corresponding to a prescribed range of the sense amplifier non-defective rate, a first combination such that the read time Tcalculated on the basis of the function f satisfies a prescribed condition. The verification support device 100 retrieves, from multiple second combination candidates of each value corresponding to a memory cell non-defective rate derived on the basis of the first combination obtained through the retrieval, a second combination such that the read time Tbased on both the sense amplifier performance value based on the first combination and the respective second combination candidates satisfies a prescribed condition.
Inventors:
Hiroyuki Higuchi
Hidetoshi Matsuoka
Hidetoshi Matsuoka
Application Number:
JP2013265844A
Publication Date:
January 10, 2018
Filing Date:
December 24, 2013
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50
Domestic Patent References:
| JP2006186150A | ||||
| JP2012103861A | ||||
| JP2010512645A |
Foreign References:
| WO2008102681A1 |
Attorney, Agent or Firm:
Akinori Sakai
Previous Patent: A manufacturing method of a guide apparatus, an image display apparatus, and a guide apparatus
Next Patent: CARRYING DEVICE
Next Patent: CARRYING DEVICE