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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPH0554681
Kind Code:
A
Abstract:

PURPOSE: To prevent outputting erroneous data even though a memory cell makes an erroneous selection by detecting an address change and controlling the output level of a sense amplifier through a P channel transistor(TR).

CONSTITUTION: A sense amplifier consists of P channel TR1 and 2, which configure a current mirror circuit, N channel TR3 and 4 which are serially connected to the N channel TRs and a complementary inverter 5 and the output of the sense amplifier is outputted through an output buffer 19. When an address detecting circuit 18 detects an address change, a P channel TR16 is turned off, the TR2 is turned off through a P channel TR17, the output level of the sense amplifier is reduced and an erroneous data output is prevented during an erroneous selection of the memory cell.


Inventors:
SATO TATSUO
Application Number:
JP21772591A
Publication Date:
March 05, 1993
Filing Date:
August 29, 1991
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C11/419; G11C16/06; G11C17/00; (IPC1-7): G11C11/419; G11C16/06
Domestic Patent References:
JPH0334197A1991-02-14
Attorney, Agent or Firm:
Uchihara Shin



 
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