Title:
不揮発性半導体メモリ装置、そのローカルロウデコーダ構造、及び半導体メモリ装置、同装置でのワードライン駆動方法
Document Type and Number:
Japanese Patent JP4047001
Kind Code:
B2
Abstract:
Semiconductor memory device row decoder structures have reduced layout area. A structure for erasing memory cells coupled to a single bitline includes a single bias driver for these cells, and a plurality of local voltage level converters coupled to the bias driver. At least one word line driver is coupled to each local level converter, to erase at least one of the memory cells. A global word line is also coupled to the word line driver. A method for erasing these memory cells includes biasing the local level converter, for powering in turn a component of the word line driver. In addition, an existing global word line driver powers another component of the word line driver, thus resulting in reduced design requirements for the local level converter.
Inventors:
Lee
Lee Noboru
Lee Noboru
Application Number:
JP2001390451A
Publication Date:
February 13, 2008
Filing Date:
December 21, 2001
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C16/06; G11C8/08; G11C8/10; G11C8/14; G11C16/02; G11C16/04; G11C16/08; G11C16/30
Domestic Patent References:
| JP2116094A | ||||
| JP10283789A |
Attorney, Agent or Firm:
Makoto Hagiwara