TECHNICAL LIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, a 1S-1R memory cell with non-linear ballast.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased functionality. The drive for ever-more functionality, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

Embedded memory with non-volatile memory devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. A non-volatile memory device such as magnetic tunnel junction (MTJ) memory device or resistive random access memory (RRAM) device is coupled with selector element to form a memory cell. A large collection of memory cells forms a key component of non-volatile embedded memory. However, with scaling of memory devices, the technical challenges of assembling a vast number of memory cells presents formidable roadblocks to commercialization of this technology today.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a view of a 1 selector -1 resistor (1S-1R) memory cell.

Figure 1B illustrates an example write voltage distribution for the 1S-1R memory cell.

Figure 2A illustrates an angled three-dimensional view of 1S-1R memory cells implemented as a cross-point memory array, in accordance with an embodiment of the present disclosure.

Figure 2B illustrates the IV curve for a two terminal selector in the 1S-1R memory cell in the cross-point memory array.

Figure 3 A illustrates a view of a 1S-1R memory cell having a resistive element.

Figure 3B illustrates an embodiment of the 1S-1R memory cell in which the resistive element comprises a resistor that adds a constant resistance to reduce the voltage reaching the memory element. Figure 3D illustrates an embodiment of the 1S-1R memory cell in which the resistive element comprises a non-linear ballast resistor.

Figures 4A-4C are graphs illustrating example IV curves of the non-linear ballast resistor

302D.

Figure 5 is a flow diagram representing various operations in a method of fabricating a 1 S- 1R memory cell with a resistive element in accordance with the embodiments disclosed herein.

Figures 6A and 6B are top views of a wafer and dies that include one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, in accordance with one or more of the embodiments disclosed herein.

Figure 7 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present disclosure.

Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, in accordance with one or more of the embodiments disclosed herein.

Figure 9 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

A 1S-1R memory cell with non-linear ballast is described. In the following description, numerous specific details are set forth, such as specific material and structural regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”,“below,”“bottom,” and“top” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modem IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

In accordance with an embodiment of the present disclosure, one or more embodiments are directed to structures and architectures for a one selector (lS)/one resistor (1R) memory cell with a non-linear resistive element. Such embodiments may have applications for one or more of cross-point memory, embedded non-volatile memory (eNVM), and memory arrays. Approaches described herein may be implemented to realize high performance highly scaled eNVM cells, and potentially increase monolithic integration of eNVM in system-on-chips (SoCs) of future technology nodes.

To provide context, non-volatile memory elements such as a Magnetoresistive random- access memory (MRAM), a magnetic tunnel junction (MTJ) memory element or a resistive random access memory (RRAM) element depend on a phenomenon of resistance switching to store information. The non-volatile memory element functions as a variable resistor where the resistance of the element may switch between a high resistance state and a low resistance state. A non-volatile memory element may be coupled with a selector element to form a memory cell. The selector may be a volatile switching element that is placed in series with the non-volatile memory element. A large collection of such memory cells forms a key component of non-volatile embedded memory.

As a first example, Figure 1 A illustrates a view of a 1 selector - 1 resistor (1S-1R) memory cell. Referring to Figure 1A, the 1S-1R memory cell 100 is shown comprising a selector element 102 formed on a resistive memory element 104. In one embodiment, the memory element 104 may comprise an MRAM, an RRAM, and the like. In an embodiment, a large collection of memory cells each including a selector element 102 and a memory element 104 are utilized to form a non volatile memory array. The non-volatile memory array formed by a memory cell at each intersection of a wordline and a bitline is, herein, referred to as a non-volatile cross-point memory array. A non-volatile cross-point memory array can offer significant advantages for scaling to achieve high density memory.

In one embodiment, the selector element 102 may comprise a monolayer selector element, a bilayer selector element, or a tri-layer selector element. In one embodiment, the monolayer selector element may include a material having a field-induced insulator metal transition (IMT) material layer between a bottom electrode and a top electrode. In another embodiment, the monolayer selector element may include a semiconducting oxide material layer (not shown) in place of the (IMT) layer.

In one embodiment, the bilayer selector element may comprise a first material layer and a second material layer between a bottom electrode and a top electrode. One of the first or second material layers or may comprise PN junction (P-i-N) diodes, in silicon or germanium, oxide-based diodes such as Hf02, A1203, Ti02, Ta205, and the like sandwiched between metals (e.g. TiN/Ta205/TiN, Ni/Ti02/Ni , Pt/IZO/CoO/Pt/TiN or Pt/Hf02/Zr02/TiN), silver-doped or copper-doped oxide such as Si02 or Hf02 & Zr02, vanadium (V) oxide, Ovonic threshold switching (OTS) or multicomponent chalcogenides, or a niobium oxide (NbxOy) in one embodiment. In one embodiment, the other of the first or second material layers or may comprise an IMT material or a semiconducting material layer.

Figure 1B illustrates an example write voltage distribution for the 1 S-1R memory cell. The example distribution shows that most writes to the 1 S-1R memory cell occur in a distribution range between .22 volts and .4 volts. When writing to the 1S-1R memory cell, a write voltage is applied that is greater than the high-end of the distribution range (.4 volts) to ensure that the voltage is sufficient to write a whole bit. In this example, the write voltage is approximately .45 volts. When reading the 1-1R memory cell, a read voltage is applied that is less than the low-end of the distribution range (.22 volts) so as to not accidentally write a bit to the 1S-1R memory cell. In this example, the read voltage is approximately 50 millivolts to .1 volts. As a further example, Figure 2A illustrates an angled three-dimensional view of 1S-1R memory cells implemented as a cross-point memory array, in accordance with an embodiment of the present disclosure.

Referring to Figure 2A, an integrated circuit structure 200 comprising the cross-point memory array includes a first plurality of conductive lines 202 along a first direction above a substrate. In an embodiment, the first plurality of conductive lines 202 is a plurality of bit lines. A plurality of memory cells 206 is on individual ones of the first plurality of conductive lines 204. Individual ones of the plurality of memory cells 206 include a selector element 208 and a memory element 210 in series. In one embodiment, the selector element 208 may comprise a two terminal selector. In one embodiment, the memory element 120 may comprise an MRAM, an RRAM, and the like. A second plurality of conductive lines 204 is on the plurality of memory cells 206. In an embodiment, the second plurality of conductive lines 204 is a plurality of word lines. The second plurality of conductive lines 204 is along a second direction orthogonal to the first direction.

Figure 2A also illustrates operation of the cross-point memory array. Generally, the memory cells 206 remain in a half select mode, where in one embodiment, the bit lines 202 and the word lines 204 remain at 0 V. A read operation occurs by changing a bit line voltage associated with a particular memory cell to +/-V/2 and changing a word line voltage associated with that memory cell to -/+V/2.

Figure 2B illustrates the IV curve for a two terminal selector in the 1S-1R memory cell in the cross-point memory array. Generally, the IV curve shows that the selector element 208 has a very high resistance and at a very low current. However, as the selector turns on, the selector jumps to a very high current and becomes low resistance. A problem may arise when attempting to read the MRAM memory element 210 when the threshold voltage (VT) for the selector element 208 is approximately .5 to .6 volts because at this voltage, the VT may unintentionally write to the MRAM memory element 200 (see Figure 1B). In other words, once the VT reaches approximately .5 volts, the selector element 208 spikes on and provides the voltage across the memory element 210 that writes a bit. This creates a read disturb situation because is there is no way to perform a low voltage read when the MRAM read voltage is less than 50 to 100 millivolts.

According to the disclosed embodiments, the read disturb may be avoided by adding a resistive element to the memory cell 206, as shown in Figure 3A. Figure 3A illustrates a view of a 1S-1R memory cell 300A having a resistive element 302A. In one embodiment, the resistive element 302A is in series with the selector element 102 and the memory element 104. Although in the embodiment shown, the resistive element 302A is located in a position between the selector element 102 and the memory element 104, the resistive element 302A may be located anywhere in series with the selector element 102 and the memory element 104 as long as the resistive element 302A is located in the cross-point node. More specifically, the resistive element 304 may be also located above the selector element 102 or below the memory element 104.

According to one aspect of the disclosed embodiments, the resistive element 302A may be implemented in a variety of ways.

Figure 3B illustrates an embodiment of the 1S-1R memory cell 300B in which the resistive element comprises a resistor 302B. Figure 3C illustrates an embodiment of the 1S-1R memory cell 300B in which the resistive element comprises a thin-film ballast resistor 302C. Both the resistor 302B and the thin-film ballast resistor 302C add a constant resistance in order to reduce the voltage reaching the memory elements 104A and 104B, respectively. Both the resistor 302B and the thin-film ballast resistor 302C allow the selector element 102B 102C to turn on, but allow the selector element 102B 102C to have a high resistance, resulting in a low voltage across the MRAM during a read operation.

Referring to the embodiments shown in Figures 3B and 3C, when the VT reaches approximately .5 volts during a read operation and the selector element 102B 102C turns on, the resistance supplied by the resistor 302B or the thin-film ballast resistor 302C is configured to reduce the voltage across the memory element 104B 104C to approximately 50 millivolts to avoid the read disturb problem. The write voltage has to be increased accordingly. If, for example, the resistor 302B and the thin-film ballast resistor 302C both provide a constant 15K of resistance, then the VCC of the cross-point memory array would need to be increase to approximately 5V to 7V in order to overcome the resistance and write a bit to the memory element 104B 104C.

Referring to Figure 3C, in one embodiment, the thin-film ballast resistor 302C may comprise thin film semiconductor materials including amorphous silicon, polysilicon, germanium (Ge), silicon germanium (SiGe), III-V compound semiconductors, indium gallium zinc oxide (IGZO), and zinc oxide (ZnO), a metal film, and a resistive metal. In one embodiment, the thin- film ballast resistor 302C may have a structure of a lightly doped semiconductor film having a resistance range of 1K to 20K.

Figure 3D illustrates a further embodiment of the 1S-1R memory cell 300D in which the resistive element comprises anon-linear ballast resistor 302D. The non-linear ballast resistor 302D is provided for cross-point applications in which a high VCC may be undesirable. The non-linear ballast resistor 302D has a high resistance at low bias during a read operation, and a low resistance at a high bias during a write operation. During the read operation, the high resistance of the non linear ballast resistor 302D limits the snap-back voltage from the selector element 102D when the selector element 102D snaps on in response to the VT. When the VT biases up during a write operation, the resistance of the non-linear ballast resistor 302D reduces nonlinearly. Therefore, in order to write a bit, the VCC of the cross-point memory array only needs to increase to IV or 1 5V, for example.

Referring to Figure 3D, in one embodiment, the non-linear ballast resistor 302C may comprise thin film semiconductor materials including amorphous silicon, polysilicon, germanium (Ge), silicon germanium (SiGe), III-V compound semiconductors, indium gallium zinc oxide (IGZO), and zinc oxide (ZnO), a metal film, and a resistive metals. In one embodiment, the non linear ballast resistor 302D may comprise multiple thin film semiconductor material layers. In one embodiment, the non-linear ballast resistor 302D has a structure that is diodic (p+/p-/p— /p+) or (n+/n-/n— /n) to create non-linearity. For example, in one embodiment, the non-linear ballast resistor 302D may comprise four layers including a first layer p+ poly-Si, a second layer of p- poly-Si layer, a third layer p— poly-Si, and a fourth layer of p+ poly-Si. In one embodiment, the non-linear ballast resistor 302D has a resistance range of 1K to 20K.

In one embodiment, for a read operation the non-linear ballast resistor 302D enables the read voltage on the memory element 104 to range from 20 millivolts to 150 millivolts. In one embodiment, the write voltage on the memory element 104 may range from 3V to 1.5V. At a higher voltages, the non-linear ballast resistor 302D becomes increasingly conductive so that the resistance is less than 5kv.

Figures 4A-4C are graphs illustrating example IV curves of the non-linear ballast resistor 302D. Figures 4A-4C shows that the non-linear ballast resistor 302D can be tuned based on selected doping levels and materials so that the range of resistance and nonlinearity can be engineered to suit a particular application.

At +-.5 VT, which triggers the selector element, the non-linear ballast resistor 302D has a relatively high resistance and then decreases rapidly beyond that to allow higher voltages to reach the MRAM. For example, during a write when the bias increases to 1.5V, the non-linear ballast resistor 302D becomes increasingly conductive such that most of that voltage reaches the MRAM at resistivity of 3K-4K.

Figure 5 is a flow diagram representing various operations in a method of fabricating a lS-lR memory cell with a resistive element in accordance with the embodiments disclosed herein. The process may include forming a bit line in an opening in a dielectric layer (block 500). In an embodiment, the bit line is formed in an opening in the dielectric layer above a substrate. The substrate may include a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI). In another embodiment, substrate may include other semiconductor materials such as germanium, silicon germanium or a suitable group III-N or a group III-V compound.

In an embodiment, the bit line is formed in the dielectric layer by a damascene or a dual damascene process that is well known in the art. In an embodiment, the bit line includes a barrier layer, such as titanium nitride, ruthenium, tantalum, tantalum nitride, and a fill metal, such as copper, tungsten. In another embodiment, the wordline 500 includes a layer of a single material such as TiN or TaN. In an embodiment, the bit line is fabricated using a subtractive etch process when materials other than copper are utilized. In one such embodiment, the bit line includes a material such as but not limited to titanium nitride, ruthenium, tantalum, tantalum nitride. In an embodiment, the dielectric layer includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the dielectric layer has an uppermost surface substantially co-planar with an uppermost surface of the bit line. In an embodiment, the dielectric layer has a total thickness between 70nm-300nm. In an embodiment, bit line is electrically connected to a circuit element such as an access transistor (not shown). Logic devices such as access transistors may be integrated with memory devices such as a MTJ device to form embedded memory.

A memory material layer stack, a resistive element layer stack, and a selector material layer stack are formed in any order over the bit line (block 502). For example, the resistive element layer stack may be deposited either over the bit line prior to the memory material layer stack, on the memory material stack, or on the selector material layer stack. In an embodiment, the memory material layer stack and the resistive element layer stack is blanket deposited on the bit line using a Physical vapor deposition (PVD) process. In an embodiment, if the memory material layer stack includes layers for an MTJ memory element the memory material layer stack is subjected to an annealing process performed at a temperature between 300-400 degrees Celsius. In an embodiment, and the selector material layer stack are respectively blanket deposited by an evaporation process, an atomic layer deposition (ALD) process or by chemical vapor deposition (CVD) process. In an embodiment, the chemical vapor deposition process is enhanced by plasma techniques such as RF glow discharge (plasma enhanced CVD) to increase the density and uniformity of the film. In an embodiment, an uppermost layer of selector material layer stack may include an uppermost electrode layer that ultimately acts as a hardmask.

A lithography step is performed that forms a photoresist mask on an uppermost surface of the selector material layer stack (block 504). In an embodiment, the photoresist mask is formed at a minimum size required for either the selector element or the memory element, and defines a location where a memory cell will be subsequently formed. In the embodiment shown, the photoresist mask is formed to the minimum size requirement of the selector element, since the selector element is over the memory element. In one embodiment, example minimum sizes for the resist could be in the range of 10 nm - 100 nm.

The selector material layer stack, the resistive element layer stack, and the memory material layer stack are then patterned in alignment with the photoresist mask (block 506). In an embodiment, a plasma etch process is utilized to pattern the selector material layer stack, the resistive element layer stack, and the memory material layer stack down to a conductive electrode layer to form the selector element 102, resistive element 302, and the memory element 104. Selector element 102, resistive element 302, and the memory element 104 are herein referred to as an active memory cell/device (as shown in Figures 2A and 3A-3D). In one embodiment, the memory element 104 may be above the selector element 102.

A second dielectric layer is deposited over the selector element and word line is patterned over the second dielectric layer (block 508). The memory cell may be completed by removing the photoresist mask and then forming the second dielectric layer on the bit line and on the active memory device (on the hardmask, on sidewalls of the selector element, resistive element and memory element). The second dielectric letter is planarized to expose an uppermost surface of the selector element. Thereafter, the word line is patterned on the uppermost surface of the selector element and on the uppermost surface of the second dielectric layer to complete formation of the memory cell. In an embodiment, the word line may comprise conductive material such as W, TiN, TaN or Ru. In an embodiment, the word line is formed by using a dual damascene process (not shown) and includes a barrier layer such as Ru, Ta or Ti and a fill metal such as W or Cu.

It is to be appreciated that the layers and materials described in association with embodiments herein are typically formed on or above an underlying semiconductor substrate, e.g., as FEOL layer(s). In other embodiments, the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s). In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, structures described herein may be fabricated on underlying lower level back end of line (BEOL) interconnect layers. For example, in one embodiment, an embedded non-volatile memory structure is formed on a material composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In a particular embodiment, an embedded non-volatile memory structure is formed on a low-k dielectric layer of an underlying BEOL layer.

In an embodiment, interconnect lines (and, possibly, underlying via structures) described herein are composed of one or more metal or metal-containing conductive structures. The conductive interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the interconnect lines includes a barrier layer and a conductive fill material. In an embodiment, the barrier layer is composed of a metal nitride material, such as tantalum nitride or titanium nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof.

Interconnect lines described herein may be fabricated as a grating structure, where the term “grating” is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have conductive lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach.

In an embodiment, ILD materials described herein are composed of or include a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si02)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

The integrated circuit structures described herein may be included in an electronic device. As an example of one such apparatus, Figures 6A and 6B are top views of a wafer and dies that include one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, in accordance with one or more of the embodiments disclosed herein.

Referring to Figures 6A and 6B, a wafer 600 may be composed of semiconductor material and may include one or more dies 602 having integrated circuit (IC) structures formed on a surface of the wafer 600. Each of the dies 602 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, such as described above. After the fabrication of the semiconductor product is complete, the wafer 600 may undergo a singulation process in which each of the dies 602 is separated from one another to provide discrete“chips” of the semiconductor product. In particular, structures that include embedded non-volatile memory structures having an independently scaled selector as disclosed herein may take the form of the wafer 600 (e.g., not singulated) or the form of the die 602 (e.g., singulated). The die 602 may include one or more embedded non-volatile memory structures based independently scaled selectors and/or supporting circuitry to route electrical signals, as well as any other IC components. In some embodiments, the wafer 600 or the die 602 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 602. For example, a memory array formed by multiple memory devices may be formed on a same die 602 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

Figure 7 illustrates a block diagram of an electronic system 700, in accordance with an embodiment of the present disclosure. The electronic system 700 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 700 may include a microprocessor 702 (having a processor 704 and control unit 706), a memory device 708, and an input/output device 710 (it is to be appreciated that the electronic system 700 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 700 has a set of instructions that define operations which are to be performed on data by the processor 704, as well as, other transactions between the processor 704, the memory device 708, and the input/output device 710. The control unit 706 coordinates the operations of the processor 704, the memory device 708 and the input/output device 710 by cycling through a set of operations that cause instructions to be retrieved from the memory device 708 and executed. The memory device 708 can include a non-volatile memory cell as described in the present description. In an embodiment, the memory device 708 is embedded in the microprocessor 702, as depicted in Figure 7. In an embodiment, the processor 704, or another component of electronic system 700, includes one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, such as those described herein.

Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more 1S-1R memory cells with a resistive elements, in accordance with one or more of the embodiments disclosed herein.

Referring to Figure 8, an IC device assembly 800 includes components having one or more integrated circuit structures described herein. The IC device assembly 800 includes a number of components disposed on a circuit board 802 (which may be, e.g., a motherboard). The IC device assembly 800 includes components disposed on a first face 840 of the circuit board 802 and an opposing second face 842 of the circuit board 802. Generally, components may be disposed on one or both faces 840 and 842. In particular, any suitable ones of the components of the IC device assembly 800 may include a number of embedded non-volatile memory structures having a 1S- 1R memory cell with a resistive element, such as disclosed herein.

In some embodiments, the circuit board 802 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 802. In other embodiments, the circuit board 802 may be a non-PCB substrate.

The IC device assembly 800 illustrated in Figure 8 includes a package-on-interposer structure 836 coupled to the first face 840 of the circuit board 802 by coupling components 816. The coupling components 816 may electrically and mechanically couple the package-on- interposer structure 836 to the circuit board 802, and may include solder balls (as shown in Figure 8), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 836 may include an IC package 820 coupled to an interposer 804 by coupling components 818. The coupling components 818 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 816. Although a single IC package 820 is shown in Figure 8, multiple IC packages may be coupled to the interposer 804. It is to be appreciated that additional interposers may be coupled to the interposer 804. The interposer 804 may provide an intervening substrate used to bridge the circuit board 802 and the IC package 820. The IC package 820 may be or include, for example, a die (the die 702 of Figure 7B), or any other suitable component. Generally, the interposer 804 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 804 may couple the IC package 820 (e.g., a die) to a ball grid array (BGA) of the coupling components 816 for coupling to the circuit board 802. In the embodiment illustrated in Figure 8, the IC package 820 and the circuit board 802 are attached to opposing sides of the interposer 804. In other embodiments, the IC package 820 and the circuit board 802 may be attached to a same side of the interposer 804. In some embodiments, three or more components may be interconnected by way of the interposer 804.

The interposer 804 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 804 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 804 may include metal interconnects 810 and vias 808, including but not limited to through-silicon vias (TSVs) 806. The interposer 804 may further include embedded devices 814, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 804. The package-on-interposer structure 836 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 800 may include an IC package 824 coupled to the first face 840 of the circuit board 802 by coupling components 822. The coupling components 822 may take the form of any of the embodiments discussed above with reference to the coupling components 816, and the IC package 824 may take the form of any of the embodiments discussed above with reference to the IC package 820.

The IC device assembly 800 illustrated in Figure 8 includes a package-on-package structure 834 coupled to the second face 842 of the circuit board 802 by coupling components 828. The package-on-package structure 834 may include an IC package 826 and an IC package 832 coupled together by coupling components 830 such that the IC package 826 is disposed between the circuit board 802 and the IC package 832. The coupling components 828 and 830 may take the form of any of the embodiments of the coupling components 816 discussed above, and the IC packages 826 and 832 may take the form of any of the embodiments of the IC package 820 discussed above. The package-on-package structure 834 may be configured in accordance with any of the package-on-package structures known in the art.

Figure 9 illustrates a computing device 900 in accordance with one implementation of the disclosure. The computing device 900 houses a board 902. The board 902 may include a number of components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processor 904.

Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, in accordance with implementations of embodiments of the disclosure. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 900 may contain an integrated circuit die that includes one or more embedded non-volatile memory structures having a 1S-1R memory cell with a resistive element, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

Thus, embodiments described herein include embedded non-volatile memory structures having 1S-1R memory cell with a resistive element elements.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example embodiment 1 : An integrated circuit structure includes a first conductive line along a first direction. A memory cell is on the first conductive line, wherein the memory cell comprises: a selector element, a memory element, and a resistive element in series with the selector element and the memory element. A second conductive line on the memory cell along a second direction orthogonal to the first direction.

Example embodiment 2: The integrated circuit structure of example embodiment 1, wherein comprises one of an MRAM and an RRAM.

Example embodiment 3: The integrated circuit structure of example embodiment 1 or 2, wherein the resistive element is located in one of a position: between the selector element and the memory element, above the selector element, and below the memory element. Example embodiment 4: The integrated circuit structure of example embodiment 1, 2 or

3, wherein the resistive element comprises a non-linear ballast resistor, wherein during a write operation, a resistance of the non-linear ballast resistor reduces nonlinearly.

Example embodiment 5: The integrated circuit structure of example embodiment 4, wherein the non-linear ballast resistor comprises at least one of: amorphous silicon, polysilicon, germanium, silicon germanium, a III-V compound semiconductor, indium gallium zinc oxide, and zinc oxide, a metal film, and a resistive metal.

Example embodiment 6: The integrated circuit structure of example embodiment 4 or 5, wherein the non-linear ballast resistor comprises multiple thin film semiconductor material layers.

Example embodiment 7: The integrated circuit structure of example embodiment 6, wherein the non-linear ballast resistor has a structure that is diodic (p+/p-/p— /p+) or (n+/n-/n— /n) to create non-linearity.

Example embodiment 8: The integrated circuit structure of example embodiment 4, 5, 6 or 7, wherein the non-linear ballast resistor has a resistance range of 1K to 20K.

Example embodiment 9: The integrated circuit structure of example embodiment 1 or 2, wherein the resistive element comprises one of a resistor and a thin film ballast resistor that provides a constant resistance in order to reduce a voltage reaching the memory element.

Example embodiment 10: The integrated circuit structure of example embodiment 9, wherein the thin-film ballast resistor comprises at least one of: amorphous silicon, polysilicon, germanium, silicon germanium, a III-V compound semiconductor, indium gallium zinc oxide, and zinc oxide, a metal film, and a resistive metal.

Example embodiment 11: The integrated circuit structure of example embodiment 9 or 10, wherein the thin-film ballast resistor comprises a doped semiconductor film having a resistance range of 1K to 20K.

Example embodiment 12: The integrated circuit structure of example embodiment 1, 2, 3,

4, 5, 6, 7, 8, 9, 10 or 11, wherein the memory cell is implemented as a cross-point memory array, and wherein the first conductive line comprises a bit line and the second conductive line comprises a word line.

Example embodiment 13: An integrated circuit structure includes a plurality of first conductive lines along a first direction above a substrate. A plurality of 1S-1R memory cells is on individual ones of the first plurality of conductive lines, wherein individual ones of the plurality of memory cells comprise a selector element, a memory element, and a ballast resistor in series with the selector element and the memory element. A plurality of second conductive lines is along a second direction orthogonal to the first direction.

Example embodiment 14: The integrated circuit structure of example embodiment 13, wherein comprises one of an MR AM and an RRAM.

Example embodiment 15: The integrated circuit structure of example embodiment 13 or 14, wherein the resistive element is located in one of a position: between the selector element and the memory element, above the selector element, and below the memory element.

Example embodiment 16: The integrated circuit structure of example embodiment 13, 14, or 15, wherein the resistive element comprises a non-linear ballast resistor, wherein during a write operation, a resistance of the non-linear ballast resistor reduces nonlinearly.

Example embodiment 17: The integrated circuit structure of example embodiment 16, wherein the non-linear ballast resistor comprises at least one of: amorphous silicon, polysilicon, germanium, silicon germanium, a III-V compound semiconductor, indium gallium zinc oxide, and zinc oxide, a metal film, and a resistive metal.

Example embodiment 18: The integrated circuit structure of example embodiment 16 or 17, wherein the non-linear ballast resistor comprises multiple thin film semiconductor material layers.

Example embodiment 19: The integrated circuit structure of example embodiment 18, wherein the non-linear ballast resistor has a structure that is diodic (p+/p-/p— /p+) or (n+/n-/n— /n) to create non-linearity.

Example embodiment 20: The integrated circuit structure of example embodiment 7, wherein the non-linear ballast resistor has a resistance range of 1K to 20K.

Example embodiment 21 : The integrated circuit structure of example embodiment 13 or 14, wherein the resistive element comprises one of a resistor and a thin film ballast resistor that provides a constant resistance in order to reduce a voltage reaching the memory element.

Example embodiment 22: The integrated circuit structure of example embodiment 21, wherein the thin-film ballast resistor comprises at least one of: amorphous silicon, polysilicon, germanium, silicon germanium, a III-V compound semiconductor, indium gallium zinc oxide, and zinc oxide, a metal film, and a resistive metal.

Example embodiment 23: The integrated circuit structure of example embodiment 21 or 22, wherein the thin-film ballast resistor comprises a doped semiconductor film having a resistance range of 1K to 20K.

Example embodiment 24: A method of fabricating an integrated circuit device includes forming a bit line in an opening in a dielectric layer; forming a memory material layer stack, a resistive element layer stack, and a selector material layer stack in any order over the bit line; performing a lithography step that forms a photoresist mask on an uppermost surface of the selector material layer stack; patterning the selector material layer stack, the resistive element layer stack, and the memory material layer stack in alignment with the photoresist mask to form a selector element, a resistive element, and a memory element; and depositing a second dielectric layer over the selector element and patterning a word line over the second dielectric layer.

Example embodiment 25 : The memory structure of example embodiment 24 forming the resistive element as a non-linear ballast resistor and forming the memory element as one of an MR AM and an RRAM.