Inventors: Arsen Terterian

Tommaso Cilento

BACKGROUND

[0001] Embodiments of the invention relate to methods and systems for improving the transformation between representations of integrated circuits.

SUMMARY

[0002] One aspect of the technology is a non-transitory computer readable medium having stored thereon a plurality of instructions, which when executed by a processor, transforms a first representation of an integrated circuit undergoing processing into a second representation of the integrated circuit undergoing processing, the second representation of the integrated circuit undergoing processing including additional dopants relative to the first representation of the integrated circuit undergoing processing, comprising the instructions that perform:

[0003] performing process simulation of a first addition of a first dopant under a first set of process conditions to generate a one-dimensional lateral profile of the first dopant and a one-dimensional depth profile of the first dopant;

[0004] generating a two-dimensional lateral dopant profile from adding the first dopant under the first set of process conditions with a first mask corresponding to the first dopant, by convolving the first mask with a lateral diffusion function in two dimensions, the lateral diffusion function customized with spreading data from the one-dimensional lateral profile; and

[0005] generating a three-dimensional dopant distribution from adding the first dopant under the first set of process conditions with the mask, by combining the two- dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant.

[0006] In one embodiment, the process simulation is performed with another mask different from the first mask.

[0007] In one embodiment, the three-dimensional dopant distribution conserves a quantity of the first dopant. [0008] In one embodiment, the first set of conditions are end-of-process conditions that incorporate other thermal processes subsequent to the first addition of the first dopant, the other thermal processes associated with at least one of another addition of the first dopant and an addition of another dopant.

[0009] In one embodiment, the spreading data is a parameter generated by fitting the one-dimensional lateral profile to at least an error function erf.

[0010] In one embodiment, the one-dimensional lateral profile is selected from results of the process simulation at a surface depth.

[0011] In one embodiment, the two-dimensional lateral dopant profile differs for field oxidation and hard mask oxidation, and the one-dimensional depth profile differs for field oxidation and hard mask oxidation.

[0012] In one embodiment, the lateral diffusion function is a Gaussian.

[0013] In one embodiment, the spreading data is a standard deviation.

[0014] In one embodiment, the three-dimensional dopant distribution generated with the mask being non-rectangular, has results within about 10% of a complete 3D simulation.

[0015] In one embodiment, the three-dimensional dopant distribution generated with the mask having an opening dimension of about 1-4 microns, has results within about 10% of a complete 3D simulation.

[0016] In one embodiment, the data processor is further configured to:

[0017] split the first mask into a second mask and a third mask, the second mask overlapping with an oxidation mask such as a LOCOS mask, and the third mask not overlapping with the oxidation mask such as the LOCOS mask, and separate convolutions with different lateral diffusion functions are performed with the second mask and the third mask.

[0018] One aspect of the technology is a non-transitory computer readable medium having stored thereon a plurality of instructions, which when executed by a processor, transforms a first representation of an integrated circuit undergoing processing into a second representation of the integrated circuit undergoing processing, the second representation of the integrated circuit undergoing processing including additional dopants relative to the first representation of the integrated circuit undergoing processing, comprising the instructions that perform:

[0019] performing process simulation of a first addition of a first dopant under a first set of process conditions to generate a one-dimensional lateral profile of the first dopant and a one-dimensional depth profile of the first dopant; [0020] generating a two-dimensional lateral dopant profile from adding the first dopant under the first set of process conditions with a first mask corresponding to the first dopant, using at least a diffusion equation, the diffusion equation customized with diffusion length data from the one-dimensional lateral profile; and

[0021] generating a three-dimensional dopant distribution from adding the first dopant under the first set of process conditions with the mask, by combining the two- dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant.

[0022] One aspect of the technology is a non-transitory computer readable medium having stored thereon a plurality of instructions, which when executed by a processor, transforms a first representation of an integrated circuit undergoing processing into a second representation of the integrated circuit undergoing processing, the second representation of the integrated circuit undergoing processing including additional dopants relative to the first representation of the integrated circuit undergoing processing, comprising the instructions that perform:

[0023] accessing a one-dimensional lateral profile of a first dopant and a one- dimensional depth profile of the first dopant, the one-dimensional lateral profile representative of a first addition of the first dopant under a first set of process conditions;

[0024] accessing a two-dimensional lateral dopant profile of the first dopant, the two- dimensional lateral dopant profile representative of adding the first dopant under the first set of process conditions with a first mask corresponding to the first dopant, wherein two-dimensional lateral dopant profile is a result of convolving the first mask with a lateral diffusion function in two dimensions, the lateral diffusion function customized with spreading data from the one- dimensional lateral profile; and

[0025] generating a three-dimensional dopant distribution from adding the first dopant under the first set of process conditions with the mask, by combining the two- dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant.

[0026] Another aspect of the invention is a system for simulating integrated circuit processing, comprising a memory and a data processor coupled to the memory. The data processor is configured to transform a first representation of an integrated circuit undergoing processing into a second representation of the integrated circuit undergoing processing. The second representation of the integrated circuit undergoing processing includes additional dopants relative to the first representation of the integrated circuit undergoing processing. The data processor performs steps as described herein. [0027] Another aspect of the technology method for simulating integrated circuit processing as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS:

[0028] Figure 1 is a simplified process flow of the improved simulation of a 3D fabrication process.

[0029] Figure 2 is a simplified process flow showing more detail on the step of completing a database in Figure 1.

[0030] Figure 3 is a simplified process flow showing more detail on the step of performing 2D process simulation in Figure 1.

[0031] Figure 4 shows a vertical 2D process simulation, and an example of generating test ID lateral and ID depth profiles.

[0032] Figure 5 shows examples of extracting lateral spreading parameter from test ID lateral profiles.

[0033] Figure 6 is a simplified process flow showing more detail on the step of completing 3D dopant distributions in Figure 1.

[0034] Figure 7 is a simplified process flow showing more detail on the step of generating 3D dopant distributions in Figure 6.

[0035] Figure 8 is a simplified block diagram of a computer system that can be used to implement aspects of the invention.

[0036] Figure 9 is a simplified representation of an illustrative integrated circuit design flow.

[0037] Figure 10 is a set of graphs showing the effects of remixing diffusion profiles.

[0038] Figure 11 is a set of concentration graphs showing the effects of remixing diffusion profiles.

[0039] Figure 12 shows the extraction of a decay length parameter from ID lateral profiles.

[0040] Figures 13a-13e show perspective views of part of a lithographic process flow and a flat 2D slice.

[0041] Figure 14 shows an initial dopant concentration in connection with Figures 13a-e.

[0042] Figures 15a-c show one embodiment of generating a 2D lateral profile by convolving a mask image with a Gaussian. [0043] Figure 16 shows the 3D mesh with implanted dopant concentrations.

[0044] Figures 17a-e show one embodiment of generating a 2D lateral profile by using a solution of a diffusion equation with the mask as an initial condition.

[0045] Figure 18 shows the 2D mesh with implanted dopant concentrations.

[0046] Figure 19 is a simplified process flow showing more detail on the step of completing 3D dopant distributions, similar to Figure 6 but based on diffusion rather than convolution.

DETAILED DESCRIPTION

[0047] The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0048] Figure 1 is a simplified process flow of the improved simulation of a 3D fabrication process.

[0049] Broadly, the process flow is divided into the steps of building a database of process information 10, and completing a 3D dopant distribution based on the database 20. In more detail, in step 10 the database includes lateral spreading parameters and ID depth profiles for all implants of all dopants. In more detail, in step 20 the 3D dopant distributions are built based on the database and the masks of the layout. Step 10 is shown in more steps in Figure 2. Step 20 is shown in more steps in Figure 6.

[0050] Figure 2 is a simplified process flow showing more detail on the step of completing a database in Figure 1.

[0051] In 22, a particular implant of a particular dopant is chosen. The implants can be elements on the periodic table or compounds thereof. Alternatively, this step can be the choice of a particular oxidation step.

[0052] In 24, 2D process simulation is performed for the particular implant of the particular dopant. Alternatively, the 2D process simulation is performed for the particular oxidation. Step 24 is shown in more detail in Figure 3. In another embodiment, a 3D process simulation is performed, and a 2D vertical slice is extracted, which is another way to perform 2D process simulation, though more computationally expensive.

[0053] In 26, a ID lateral profile is extracted from the 2D process simulation. In 28, a

ID depth profile is extracted from the 2D process simulation. An example is shown at Figure 4. In one embodiment, the 2D process simulation can be separate simulations such that ID lateral profile and the ID depth profile are extracted from different 2D process simulations. However, the embodiment of extracting the ID lateral profile and the ID depth profile from the same 2D process simulation requires fewer processing resources. Either embodiment is an example of performing process simulation to generate a ID lateral profile of a dopant and a ID depth profile of the first dopant.

[0054] In 30, a lateral spreading parameter is extracted from the ID lateral profile. An example is shown in Figure 5.

[0055] In 32, the lateral spreading profile and the ID depth profile are stored in one or more databases. In another embodiment, the ID lateral profile is stored instead of, or in addition to, the lateral spreading parameter. If the ID lateral profile is stored, extraction of the lateral spreading parameter can be delayed until a later step, no later than when the lateral spreading parameter is needed.

[0056] In 34, the process flow loops back for other implants of the same dopant.

[0057] In 36, the process flow loops back for other dopants.

[0058] In another embodiment, the process at least partly interleaves, and/or performs at least partly concurrently, calculations for different implants of the same dopant or different dopants.

[0059] In 38, the database is completed of lateral spreading parameters and ID depth profiles for all implants of all dopants, and all oxidations. In yet another embodiment, the database stores the 2D process simulations, and extracts the lateral and vertical profiles and the lateral spreading parameter later.

[0060] Various embodiments can reorder, add, remove, or change steps in the process flow.

[0061] Figure 3 is a simplified process flow showing more detail on the step of performing 2D process simulation in Figure 1. [0062] In 42, end-of-process conditions are generated for a particular implant of a particular dopant. Alternatively, end-of-process conditions are generated for a particular oxidation step. The end-of-process conditions consider not only temperatures and durations of thermal processes immediately after the particular implant of the particular dopant, but also temperatures and durations of subsequent thermal processes.

[0063] In 44, test structures are used for generating the test lateral and test depth profiles.

In one example, the test structures are based on basic polygonal shapes such as rectangular masks. The rectangular opening of the mask results in sufficient data to extract test lateral and test depth profiles. Other embodiments have different sized or shaped mask openings. Beyond the extracted test lateral and test depth profiles, the remainder of the 2D simulation results are discarded. Although more complicated masks may be used also, such complicated masks require more complicated 2D simulation that is unnecessary for the purpose of extracting the test lateral and test depth profiles.

[0064] Different masks are used in different stages of the overall simulation. Step 44 uses a first mask to generate basic data. An end result of this overall technology is a simulation of a 2D doping distribution from adding a dopant through a second mask, taking advantage of the basic data gained with the first mask. The first and second masks are different.

[0065] In 46, 2D simulation is performed with test structures from 44 under end-of- process conditions from 42.

[0066] Figure 4 shows a vertical 2D process simulation, and an example of generating test ID lateral and ID depth profiles.

[0067] Shown are an example test ID lateral profile 52 and an example test ID depth profile. The purpose of this 2D process simulation was to generate the test ID lateral and test ID depth profiles for a particular implant of a particular dopant. Accordingly, the remainder of the results of this 2D process simulation can be discarded.

[0068] The example test ID lateral profile 52 is taken along the surface of the substrate.

The example test ID depth profile can be taken generally from about the middle of the mask opening. The figure of the 2D slice does not show the right portion of the mask opening, which during simulation can be omitted to take advantage of symmetry for faster simulation results.

[0069] Figure 5 shows examples of extracting lateral spreading parameter from test ID lateral profiles. [0070] The graph includes lateral profiles 66 and 68 extracted from respective 2D process simulations. In one embodiment, lateral spreading parameters are extracted from lateral profiles 66 and 68 by curve fitting an error function erf of the following form, with another scaling constant (not shown) for the maximum concentration:

[0072] A respective lateral spreading parameter, in this case the standard deviation, is extracted after performing a curve fit between erf(x) with various candidate standard deviations. The curve fit of 62 to 66 generates a lateral spreading parameter for the lateral profile 66. The curve fit of 64 to 68 generates a lateral spreading parameter for the lateral profile 68. A single quantity, the lateral spreading parameter σ, characterizes an entire curve.

[0073]

[0074] Figure 6 is a simplified process flow showing more detail on the step of completing 3D dopant distributions in Figure 1.

[0075] In 72, a particular implant of a particular dopant is chosen. These are the same set of dopants and the same set of implants as with step 22 of Figure 2. Alternatively, a particular oxidation is chosen as with step 22 of Figure 2.

[0076] In 74, the lateral spreading parameter is accessed from the database. The lateral spreading parameter was stored in the database in 32 of Figure 2.

[0077] In 76, a 2D lateral function is generated from the lateral spreading profile. In one embodiment, the lateral spreading parameter (for example, a standard deviation) which was extracted in 30 of Figure 2, is used in a Gaussian function of the following form, with another scaling constant (not shown):

[0078] G(x,y) =— ^2σ '

2πσ

[0079] In 78, the 2D lateral function is convolved with the mask for the particular implant of the particular dopant, to generate the 2D lateral profile. Alternatively, the 2D lateral function is convolved with the mask for the particular oxidation, to generate the 2D lateral profile. [0080] Alternatively, the 2D lateral profile is obtained via another type of analytic implantation with the Gaussian function. However, analytic implantation generally requires a 3D mesh which is computationally expensive.

[0081] In 80, the ID depth profile is extracted from the database. The ID depth profile was stored in the database in 32 of Figure 2.

[0082] In 82, the 3D dopant distribution is generated from the 2D lateral profile and the

ID depth profile.

[0083] In 84, the process flow loops back for other implants of the same dopant.

[0084] In 86, the process flow loops back for other dopants.

[0085] In another embodiment, the process at least partly interleaves, and/or performs at least partly concurrently, calculations for different implants of the same dopant or different dopants.

[0086] In 88, the 3D dopant distributions are completed for all implants of all dopants, and all oxidations.

[0087] Various embodiments can reorder, add, remove, or change steps in the process flow.

[0088] In some embodiments, implants behave differently under an oxidation such as

LOCOS and active area. Accordingly, a given implant may be split into two masks: a first mask of the implant that overlaps with the oxidation such as LOCOS, and a second mask of the remainder.

[0089] In one example, the software representations of an isolation mask and an implantation mask are processed to obtain the software representation of the intersection of the isolation mask and the implantation mask. A Boolean AND operation or "*" yields the intersection, such as intersection area = isolation mask * implantation mask. This intersection area indicates where as-implanted ions hit isolation oxide such as STI or LOCOS. Subtraction of the isolation mask from the implantation mask indicates the active area of the device exposed to the ion beam, for example active area = implantation mask - isolation mask. The intersection area and active area are treated with different ID depth profiles and resulting 3D dopant distributions, despite representing the same dopant.

[0090] More generally, such Boolean manipulation of masks can take into account the shielding properties of materials that block implants. Another example is to take into account the shielding properties of gates such as polysilicon gates, for example by subtracting the gate area from the intersection area and the active area for an LDD implant. Another example is to take into account the shielding properties of spacers such as nitride spacers (such as when spacers extend the gate mask), for example by subtracting the spacer area from the intersection area and the active area.

[0091] In another embodiment, a device with a slightly different dose, such as an

NWELL dose, such as up to +/- 10% can be simulated in different ways: rescale the old dose data without having to perform more process simulation, or perform more process simulation with the changed implantation dose.

[0092] In another embodiment, the simulation generates a 2D profile. To generate the

2D dopant distribution, the ID depth profile is multiplied with a ID lateral profile. The ID lateral profile is generated by convolving the ID slice of the mask with a ID Gaussian function. The 2D dopant distribution corresponds to the region below the ID slice of the mask.

[0093] The ID Gaussian function has the following form, with another scaling constant

(not shown):

-χ

[0094] G(x,y) =— ]= e ² ^

[0095] Figure 7 is a simplified process flow showing more detail on the step of generating 3D dopant distributions in Figure 6.

[0096] In 92, for a particular implant of a particular dopant, a 3D profile is generated by multiplying the 2D lateral profile and the ID depth profile.

[0097] In 94, a 3D boundary structure is generated by boundary emulation.

[0098] In 96, the 3D profile is interpolated onto the mesh of the 3D boundary structure.

[0099] In 98, the 3D structure is completed for the particular implant of the particular dopant. Alternatively, the 3D structure is completed for the particular oxidation.

Computer System

[00100] Figure 8 is a simplified block diagram of a computer system 1 10 that can be used to implement software incorporating aspects of the present invention. While the present paper indicates individual steps carrying out specified operations, it will be appreciated that each step is actually implemented with software instructions that cause the computer system 1 10 to operate in the specified manner. The group of software instructions and data to implement a particular step, in conjunction with the processing subsystem and other components of the computer system which enable such software instructions to be executed, constitute a module which implements the particular step.

[00101] Computer system 110 typically includes a processor subsystem 1 14 which communicates with a number of peripheral devices via bus subsystem 1 12. These peripheral devices may include a storage subsystem 124, comprising a memory subsystem 126 and a file storage subsystem 128, user interface input devices 122, user interface output devices 120, and a network interface subsystem 1 16. The input and output devices allow user interaction with computer system 1 10. Network interface subsystem 1 16 provides an interface to outside networks, including an interface to communication network 1 18, and is coupled via

communication network 118 to corresponding interface devices in other computer systems. Communication network 1 18 may comprise many interconnected computer systems and communication links. These communication links may be wireline links, optical links, wireless links, or any other mechanisms for communication of information. While in one embodiment, communication network 118 is the Internet, in other embodiments, communication network 1 18 may be any suitable computer network.

[00102] The physical hardware component of network interfaces are sometimes referred to as network interface cards (NICs), although they need not be in the form of cards: for instance they could be in the form of integrated circuits (ICs) and connectors fitted directly onto a motherboard, or in the form of macrocells fabricated on a single integrated circuit chip with other components of the computer system.

[00103] User interface input devices 122 may include a keyboard, pointing devices such as a mouse, trackball, touchpad, or graphics tablet, a scanner, a touch screen incorporated into the display, audio input devices such as voice recognition systems, microphones, and other types of input devices. In general, use of the term "input device" is intended to include all possible types of devices and ways to input information into computer system 110 or onto computer network 1 18.

[00104] User interface output devices 120 may include a display subsystem, a printer, a fax machine, or nonvisual displays such as audio output devices. The display subsystem may include a cathode ray tube (CRT), a flat panel device such as a liquid crystal display (LCD), a projection device, or some other mechanism for creating a visible image. The display subsystem may also provide non visual display such as via audio output devices. In general, use of the term "output device" is intended to include all possible types of devices and ways to output information from computer system 110 to the user or to another machine or computer system.

[00105] Storage subsystem 124 stores the basic programming and data constructs that provide the functionality of certain embodiments of the present invention. For example, the various modules implementing the functionality of certain embodiments of the invention may be stored in storage subsystem 124. Some examples are a tool for generating 3D dopant distributions or 3D oxidations based on lateral spreading parameters extracted from ID test lateral profiles; and a tool for generating a database of ID vertical profiles and lateral spreading parameters. These software modules are generally executed by processor subsystem 1 14.

Storage subsystem 124 also represents storage accessible to the computer system on which the various databases mentioned herein are stored. Storage subsystem 124 can store the database of ID vertical profiles and lateral spreading profiles; and a tool for generating a database of ID vertical profiles and lateral spreading parameters. Alternatively, the tool accesses the local or remote database of ID vertical profiles and lateral spreading parameters, or in combination both generates and accesses the database.. In another embodiment some or all of the databases are located on storage accessible to the computer system via the network 118.

[00106] Memory subsystem 126 typically includes a number of memories including a main random access memory (RAM) 130 for storage of instructions and data during program execution and a read only memory (ROM) 132 in which fixed instructions are stored. File storage subsystem 128 provides persistent storage for program and data files, and may include a hard disk drive, a floppy disk drive along with associated removable media, a CD ROM drive, an optical drive, or removable media cartridges. The databases and modules implementing the functionality of certain embodiments of the invention may have been provided on a computer readable medium such as one or more CD-ROMs, and may be stored by file storage subsystem 128. The host memory 126 contains, among other things, computer instructions which, when executed by the processor subsystem 1 14, cause the computer system to operate or perform functions as described herein. As used herein, processes and software that are said to run in or on "the host" or "the computer", execute on the processor subsystem 1 14 in response to computer instructions and data in the host memory subsystem 126 including any other local or remote storage for such instructions and data.

[00107] Bus subsystem 1 12 provides a mechanism for letting the various components and subsystems of computer system 110 communicate with each other as intended. Although bus subsystem 1 12 is shown schematically as a single bus, alternative embodiments of the bus subsystem may use multiple busses.

[00108] Computer system 110 itself can be of varying types including a personal computer, a portable computer, a workstation, a computer terminal, a network computer, a television, a mainframe, a server farm, or any other data processing system or user device. Due to the ever changing nature of computers and networks, the description of computer system 110 depicted in Figure 8 is intended only as a specific example for purposes of illustrating certain embodiments of the present invention. Many other configurations of computer system 110 are possible having more or less components than the computer system depicted in Figure 8.

Integrated Circuit Manufacturing Flow

[00109] Figure 9 shows a simplified representation of an illustrative integrated circuit design flow incorporating features of the technology. At a high level, the process starts with the product idea (step 200) and is realized in an EDA (Electronic Design Automation) software design process (step 210). When the design is finalized, it can be taped-out (step 240). After tape out, the fabrication process (step 250) and packaging and assembly processes (step 260) occur resulting, ultimately, in finished integrated circuit chips (result 270).

[00110] The EDA software design process (step 210) is actually composed of a number of steps 212-230, shown in linear fashion for simplicity. In an actual integrated circuit design process, the particular design might have to go back through steps until certain tests are passed. Similarly, in any actual design process, these steps may occur in different orders and combinations. This description is therefore provided by way of context and general explanation rather than as a specific, or recommended, design flow for a particular integrated circuit.

[00111] A brief description of the components steps of the EDA software design process (step 210) will now be provided.

[00112] System design (step 212): The designers describe the functionality that they want to implement, they can perform what-if planning to refine functionality, check costs, etc.

Hardware-software architecture partitioning can occur at this stage. Example EDA software products from Synopsys, Inc. that can be used at this step include Model Architect, Saber, System Studio, and DesignWare® products.

[00113] Logic design and functional verification (step 214): At this stage, the VHDL or

Verilog code for modules in the system is written and the design is checked for functional accuracy. More specifically, the design is checked to ensure that produces the correct outputs in response to particular input stimuli. Example EDA software products from Synopsys, Inc. that can be used at this step include VCS, VERA, Design Ware®, Magellan, Formality, ESP and LED A products.

[00114] Synthesis and design for test (step 216): Here, the VHDL/Verilog is translated to a netlist. The netlist can be optimized for the target technology. Additionally, the design and implementation of tests to permit checking of the finished chip occurs. Example EDA software products from Synopsys, Inc. that can be used at this step include Design Compiler®, Physical Compiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, and Design Ware® products.

[00115] Netlist verification (step 218): At this step, the netlist is checked for compliance with timing constraints and for correspondence with the VHDL/Verilog source code. Example EDA software products from Synopsys, Inc. that can be used at this step include Formality, PrimeTime, and VCS products.

[00116] Design planning (step 220): Here, an overall floor plan for the chip is constructed and analyzed for timing and top-level routing. Example EDA software products from Synopsys,

Inc. that can be used at this step include Astro and IC Compiler products.

[00117] Physical implementation (step 222): The placement (positioning of circuit elements) and routing (connection of the same) occurs at this step. Example EDA software products from Synopsys, Inc. that can be used at this step include the Astro and IC Compiler products.

[00118] Analysis and extraction (step 224): At this step, the circuit function is verified at a transistor level, this in turn permits what-if refinement. Example EDA software products from Synopsys, Inc. that can be used at this step include AstroRail, PrimeRail, Primetime, and Star RC/XT products.

[00119] Physical verification (step 226): At this step various checking functions are performed to ensure correctness for: manufacturing, electrical issues, lithographic issues, and circuitry. Example EDA software products from Synopsys, Inc. that can be used at this step include the Hercules product.

[00120] Tape-out (step 227): This step provides the "tape out" data for production of masks for lithographic use to produce finished chips. Example EDA software products from Synopsys, Inc. that can be used at this step include the CATS(R) family of products. [00121] Resolution enhancement (step 228): This step involves geometric manipulations of the layout to improve manufacturability of the design. Example EDA software products from Synopsys, Inc. that can be used at this step include Proteus, ProteusAF, and PSMGen products.

[00122] Mask data preparation (step 230): This step provides the "tape-out" data for production of masks for lithographic use to produce finished chips. Example EDA software products from Synopsys, Inc. that can be used at this step include the CATS(R) family of products.

[00123] A typical integrated circuit manufacturing flow also includes a parallel flow, as follows:

[00124] (1) Develop individual process steps for manufacturing the integrated circuit.

This can be modeled with the Synopsys tools "Sentaurus Process", "Sentaurus Topography", and "Sentaurus Lithography". The input information here include masks or layout information, and process conditions like temperature, reactor ambient, implant energy, etc. The output information is the final geometry or doping profiles or stress distribution. Aspects of the invention can be used in this step of the manufacturing flow.

[00125] (2) Integrate the individual process steps into the complete process flow. This can be modeled with the Synopsys tool "Sentaurus Process". The input information here includes the layout information and the collection of the process steps in the appropriate sequence. The output includes the geometry, the doping profiles, and the stress distribution for the transistors and the space in between the transistors. Aspects of the invention can be used also in this step of the manufacturing flow.

[00126] (3) Analyze performance of the transistor manufactured with this process flow.

This can be done with the Synopsys tool "Sentaurus Device". The input information here includes the output of step (2) and the biases applied to transistor terminals. The output information includes the currents and capacitances for each bias combination.

[00127] (4) If necessary, modify the process steps and the process flow to achieve the desired transistor performance. This can be done iteratively by using the Synopsys tools mentioned above.

[00128] Once the process flow is ready, it can be used for manufacturing multiple circuit designs coming from various designers in various companies. The EDA flow 212-230 will be used by such designers. The parallel flow described here is used at a foundry to develop a process flow that can be used to manufacture designs coming from the designers. A combination of the process flow and the masks made from step 230 are used to manufacture any particular circuit. If the designers are at a different company, e.g. a fabless company, then usually it is the foundry that performs this parallel process flow whereas the process steps of Fig. 9 are performed typically by the fabless company. If the integrated circuit is manufactured at an IDM (integrated device manufacturer) company instead of the combination of a fabless company and a foundry, then both parallel flows described above are done at the same IDM company.

[00129] There is also a bridge between these tools and the 212-230 EDA tools. The bridge is a Synopsys tool "Seismos" that applies compact proximity models for particular circuit design and layout to obtain netlist with instance parameters for each individual transistor in the circuit as a function of its neighborhood and stress, including material conversion stress. This netlist is used in the analysis step 224.

[00130] The applicants hereby disclose in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicants indicate that aspects of the present invention may consist of any such feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

[00131] Figure 10 is a set of graphs showing the effects of remixing diffusion profiles.

[00132] Figure 11 is a set of concentration graphs showing the effects of remixing diffusion profiles, corresponding to Figure 10.

[00133] The remix operation addresses the doping artifacts appearing in the transition region between active area and isolation area.

[00134] The example shows a gate with spacers overlapping an STI (shallow trench isolation oxide). In Figure 10, profile 1002 before remix ends at the bottom of the STI to indicate zero active doping concentration within the STI region (typically oxide) because dopants are inactive in insulators. The active profile 1001 extends until the Si surface. When using these two profiles 1001 and 1002 to merge active area and isolation profiles, artifacts 1 105 and 1106 result in Figure 11, shown as an active dopant concentration abnormally dropping-off nearby the STI edges, from about 10 ¹⁷ cm ^"3 below the STI to about 5 x 10 ¹⁶ cm ^"3 in just under Si on both sides of the STL By extending the profile 1004 until Si the surface and using this profile for merging active area and isolation profiles 1003 and 1004, this artifact is addressed, as shown in 1107 and 1 108 of Figure 11. The resulting ID profile is free of the abnormal drop-off of active dopant concentration nearby the STI edges.

[00135] Alternatives of generating the 2D lateral profile are discussed as follows.

[00136] Figure 12 shows the extraction of a decay length parameter from ID lateral profiles.

[00137] The example shows lateral profiles for different dopants boron and arsenic, with respective spreading parameters, in this case decay lengths in an error function. In Figure 12, profile 164 is the simulated lateral profile of boron, and 168 is the fitted lateral profile of boron. Profile 162 is the simulated lateral profile of arsenic, and 166 is the fitted lateral profile of arsenic. The following ID fitted profile is used:

[00138] Φ(χ) = i [l + er/ ( )]

[00139] Figures 13a-13d show perspective views of part of a lithographic process flow used in several of the following figures. In Figure 13 a, photoresist is formed lithographically to cover region 302 but not region 304. In Figure 13b, silicon is etched in region 304 uncovered by the photoresist, resulting in etched region 306. In Figure 13c, the photoresist is stripped, leaving stripped region 308 and etched region 306. In Figure 13d, oxide is deposited in etched region 306 to form an oxide region 310. Figure 13e shows a flat 2D slice of Figure 13d, with stripped region 308 and oxide region 310.

[00140] Figure 14 shows an initial dopant concentration in connection with the lithographic process of Figures 13a-d and the flat 2D slice in Figure 13e. Before diffusion, the boron concentration is 10 ¹⁶ cm ^"3 in oxide region 410, and is zero in the silicon 408 of the stripped region.

[00141] Figures 15-16 show one embodiment of generating a 2D lateral profile, in which a

3D mesh is generated in order to generate the 2D lateral profile.

[00142] Figure 15a shows a sharp mask image, which indicates good results for the convolution technique. Masks generally can be broken down into basic shapes such as Figure 15a. Figure 15b shows a 2D lateral function, in this case a Gaussian function, to represent the movement of dopants, having the following form:

-χ

[00143] G(x,y) =—=e ^1(jl [00144] In which the standard deviation, σ, is the diffusion length DL over the square root of 2.

[00145] To generate the 2D lateral profile, the 2D mask or 2D photoresist resulting from the mask is convolved with the 2D lateral function. Figure 15c shows the convolution result of a Gaussian blur.

[00146] Figure 16 shows the 3D mesh with implanted dopant concentrations at various depths of the 3D mesh being determined by the Gaussian blur. The 3D mesh scale is normalized with 1 being the peak concentration.

[00147] Figures 17-18 show another embodiment of generating a 2D lateral profile, in which a 2D mesh rather than a 3D mesh can be generated in order to generate the 2D lateral profile.

[00148] Figure 17a shows a sharp mask image, which indicates good results for the diffusion technique. Masks generally can be broken down into basic shapes such as Figure 17a. Figure 17b shows a diffusion equation, to represent the movement of dopants, having the following form:

[00149] The ID diffusion formula is as follows:

[00151] in which D is the diffusion constant.

[00152] To generate the 2D lateral profile, diffusion equation solutions are used. Figure

15c shows the diffusion equation solution resulting from the initial conditions for diffusion as represented by the sharp mask image of Figure 17a.

[00153] In the example, a diffusion equation for 1 second is solved in the mask plane.

The same distribution results as with the analytic implantation alternative of Figures 15-16, provided the diffusion coefficient is constant and equals to one quarter of a diffusion length (DL).

[00154] The ID diffusion equation solution is as follows:

[00155] φ _{Μ =} [ _{1 +} erf (-!=)]

[00156] Although 1 second time is chosen for convenience, the product of the diffusion coefficient and diffusion time which equals diffusion length is more determinative of the result.

[00157] The 2D diffusion formula is as follows:

[00158] D ² C = _t →

[00160] The 2D diffusion formula presents similar solutions to the ID diffusion formula but with a cylindrical distribution.

[00161] Figure 18 shows 2D mesh with implanted dopant concentration being determined by a solution to the diffusion equation. The 2D mesh scale is normalized with 1 being the peak concentration.

[00162] Both the convolution and diffusion equation methods give identical results but the latter one is preferred because it does not require 3D meshes so it is naturally faster and more robust.

[00163] Figure 19 is a simplified process flow showing more detail on the step of completing 3D dopant distributions in Figure 1, similar to Figure 6 but based on diffusion rather than convolution.

[00164] The process flow is similar between Figures 6 and 19. However, in 76, the 2D lateral function is based on a solution to the diffusion equation. Instead of convolution, in 79 the 2D lateral profile is generated from the 2D lateral function which can be based on a solution to a diffusion equation, with initial dopant conditions based on the mask of photoresist layer based on the mask for the particular implant of the particular dopant or the mask for the particular oxidation, to generate the 2D lateral profile.

[00165] The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. In addition, and without limitation, any and all variations described, suggested or incorporated by reference in the Background section of this patent application are specifically incorporated by reference into the description herein of embodiments of the invention. In addition, any and all variations described, suggested or incorporated by reference herein with respect to any one embodiment are also to be considered taught with respect to all other embodiments. The embodiments described herein were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.