ACCESS CONTROL METHOD, ACCESS CONTROL DEVICE, AND DATA PROCESSING DEVICE

WIPO Patent Application WO/2020/095677

A1

The objective of the present invention is to enable a plurality of users to use an application processing circuit in a data processing device. An access control unit 16 is equipped with: a packet buffer 22 provided for each user; a packet identification unit 21 for storing a received packet in the corresponding packet buffer 22; a scheduling unit 25 for determining the packet buffer for which a transfer is to be made; a transfer control unit 26 which, in a condition in which reference data can be updated in an application processing circuit 17 and the packet buffer 22 determined by the scheduling unit 25 is different from the current packet buffer 22 for which a transfer is to be made, updates the current reference data to reference data corresponding to the packet buffer 22 that has been determined by the scheduling unit 25; and a buffer selection unit 23 which, when the reference data update is completed, connects the packet buffer for which it has been determined that a transfer is to be made to the packet transfer unit 24.

UKON YUTA (JP)
YOSHIDA SHUHEI (JP)
NITTA KOYO (JP)

PCT/JP2019/041481

May 14, 2020

October 23, 2019

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NIPPON TELEGRAPH & TELEPHONE (JP)

G06F13/00

CN107623834A	2018-01-23
JP2013206390A	2013-10-07

WATANABE, YOSHIKAZU ET AL.: "Acceleration Method for Network Function Virtualization Using FPGA tightly coupled with CPU", IPSJ SYMPOSIUM (DA SYMPOSIUM, 7 September 2016 (2016-09-07), pages 116 - 121

YAMAKAWA, Shigeki et al. (JP)

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