Title:
ACCUMULATOR, MULTIPLIER, AND OPERATOR CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/004783
Kind Code:
A1
Abstract:
The present application relates to the technical field of electronics, and provides an accumulator, a multiplier, and an operator circuit, used to reduce the area and power consumption of an accumulator. The accumulator comprises: W compressor layers, W being an integer greater than or equal to 1, wherein the W compressor layers comprise at least one first compressor layer, in an input array of each first compressor layer, a first array comprises a plurality of positive phase bits, a second array comprises a plurality of inverted phase bits, and each first compressor layer comprises a first compression circuit for compressing the first array and a second compression circuit for compressing the second array, that is, bits of different phases in the input array of each first compressor layer are compressed by different compression circuits.
Inventors:
FAN TUANBAO (CN)
SHI XIAOSHAN (CN)
JIANG YUEXING (CN)
JIANG MINGFENG (CN)
SHI XIAOSHAN (CN)
JIANG YUEXING (CN)
JIANG MINGFENG (CN)
Application Number:
PCT/CN2021/109751
Publication Date:
February 02, 2023
Filing Date:
July 30, 2021
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F7/50; G06F7/523
Foreign References:
| CN112596699A | 2021-04-02 | |||
| CN105528191A | 2016-04-27 | |||
| US20070244943A1 | 2007-10-18 | |||
| US20030158879A1 | 2003-08-21 | |||
| CN2019119993W | 2019-11-21 |
Other References:
KONG XIN, CHEN GANG; GONG GUOLIANG; LU HUAXIANG; MAO WENYU: "High Performance Multiply-accumulator for the Convolutional Neural Networks Accelerator", XI'AN DIANZI KE JI DAXUE XUEBAO - JOURNAL OF XIADIAN UNIVERSITY, XI'AN DIANZI KE JI DAXUE, XI'AN,, CN, vol. 47, no. 4, 31 August 2020 (2020-08-31), CN , XP093028523, ISSN: 1001-2400, DOI: 10.19665/j.issn1001-2400.2020.04.008
LIU, WEIQIANG ET AL.: "Design and Analysis of Approximate Redundant Binary Multipliers", IEEE TRANSACTIONS ON COMPUTERS, vol. 68, no. 6, 30 June 2019 (2019-06-30), XP011723015, ISSN: 0018-9340, DOI: 10.1109/TC.2018.2890222
LIU, WEIQIANG ET AL.: "Design and Analysis of Approximate Redundant Binary Multipliers", IEEE TRANSACTIONS ON COMPUTERS, vol. 68, no. 6, 30 June 2019 (2019-06-30), XP011723015, ISSN: 0018-9340, DOI: 10.1109/TC.2018.2890222
Attorney, Agent or Firm:
BEIJING ZBSD PATENT & TRADEMARK AGENT LTD. (CN)
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