BUI LONG (US)
BINKLEY JEB (US)
WO2017218876A1 | 2017-12-21 | |||
WO2007063298A1 | 2007-06-07 |
US20130162475A1 | 2013-06-27 | |||
US20120201097A1 | 2012-08-09 | |||
US5537367A | 1996-07-16 | |||
US20170209121A1 | 2017-07-27 |
CLAIMS WHAT IS CLAIMED IS: 1. An active array system, comprising: one or more processors; and a plurality of radiating elements coupled to the one or more processors, wherein the plurality of radiating elements comprise: a first group of radiating elements comprising a first number of radiating elements (Na) disposed a first distance apart (Sa); and a second group of radiating elements comprising a second number of radiating elements (Nb) disposed a second distance apart (Sb); wherein the second number of radiating elements (Nb) are configured to form an aperture spanning a length (L), and wherein the second distance (Sb) is based on a reduction factor (Mrx), the first number of radiating elements (Na), and the first distance (Sa). 2. The active array system of claim 1, wherein the first number of radiating elements (Na) is less than the second number of radiating elements (Nb). 3. The active array system of claim 1, wherein Sb is greater than one-half of a wavelength of a transmit signal associated with the first group radiating elements (Na). 4. The active array system of claim 1, where in the one or more processors are configured to process a radiation pattern comprising a plurality of lobes, and to identify a primary lobe from among the plurality of lobes for signal processing. 5. The active array system of claim 1, wherein the second group of radiating elements are configured to operate above 10 GHz. 6. The active array system of claim 1, wherein the second group of radiating elements are configured to operate between 30 GHz and 300 GHz. 7. The active array system of claim 1, wherein the first group of radiating elements (Na) are configured to operate at wavelengths between 1mm and 1cm. 8. A method comprising: transmitting a first radiation pattern using a first group of radiating elements, wherein the first group of radiating elements comprise a first number of radiating elements (Na) disposed a first distance apart (Sa); and receiving a second radiation pattern using a second group of radiating elements, wherein the second group of radiating elements comprise a second number of radiating elements (Nb) disposed a second distance apart (Sb), wherein the second number of radiating elements (Nb) are configured to form an aperture spanning a length (L), and wherein the second distance (Sb) is based on a reduction factor (Mrx), the first number of radiating elements (Na), and the first distance (Sa). 9. The method of claim 8, wherein the first number of radiating elements (Na) is less than the second number of radiating elements (Nb). 10. The method of claim 8, wherein Sb is greater than one-half of a wavelength of a transmit signal associated with the first group of radiating elements (Na). 11. The method of claim 8, further comprising: processing a radiation pattern comprising a plurality of lobes, and to identify a primary lobe from among the plurality of lobes for signal processing. 12. The method of claim 8, wherein the second group of radiating elements are configured to operate above 10 GHz. 13. The method of claim 8, wherein the second group of radiating elements are configured to operate between 30 GHz and 300 GHz. 14. The method of claim 8, wherein the first group of radiating elements (Na) are configured to operate at wavelengths between 1mm and 1cm. 15. A non-transitory computer-readable storage medium comprising instructions stored therein, which when executed by one or more processors, cause the processors to perform operations comprising: transmitting a first radiation pattern using a first group of radiating elements, wherein the first group of radiating elements comprise a first number of radiating elements (Na) disposed a first distance apart (Sa); and receiving a second radiation pattern using a second group of radiating elements, wherein the second group of radiating elements comprise a second number of radiating elements (Nb) disposed a second distance apart (Sb), wherein the second number of radiating elements (Nb) are configured to form an aperture spanning a length (L), and wherein the second distance (Sb) is based on a reduction factor (Mrx), the first number of radiating elements (Na), and the first distance (Sa). 16. The non-transitory computer-readable storage medium of claim 15, wherein the first number of radiating elements (Na) is less than the second number of radiating elements (Nb). 17. The non-transitory computer-readable storage medium of claim 15, wherein Sb is greater than one-half of a wavelength of a transmit signal associated with the first group of radiating elements (Na). 18. The non-transitory computer-readable storage medium of claim 15, where in the one or more processors are configured to process a radiation pattern comprising a plurality of lobes, and to identify a primary lobe from among the plurality of lobes for signal processing. 19. The non-transitory computer-readable storage medium of claim 15, wherein the second group of radiating elements are configured to operate above 10 GHz. 20. The non-transitory computer-readable storage medium of claim 15, wherein the second group of radiating elements are configured to operate between 30 GHz and 300 GHz. |
Equation 8: [0053] To those familiar with the art, w n are the complex valued coefficients which may be used to steer the array of N elements. Furthermore, k is the wave number vector and r n is the direction vector, in some aspects, of the inbound wave-front, and in other aspects, of the outbound wave front. In some aspects steering may be performed using analog phase shifters. In other aspects, steering may be performed using digital signal processing. [0054] The wave number vector k is used to describe the space wave established by the coherent process. To those familiar with the art, k is defined as the vector: k = [kx,ky,kz], where k x , k y and k z denote the component of the wave vector along the x, y and z axes. This can be re- factored as, k = 2*pi/l * P, where P is a unit projection vector. Therefore, the magnitude of k is defined as (2*pi/l) 2 *|P| 2 = |k| 2 . Because P is a unit projection vector, |P| 2 = 1 thus |k| 2 = (2*pi/l) 2 ® |k| = 2*pi/l. [0055] When referring to the wave number, as opposed to the wave number vector, i.e. k vs. k, the magnitude of k, the wave number assumes the value of the magnitude of the wave number vector, i.e. k=|k|=2*pi/l without departing from the scope of the invention. [0056] Whereas only three dimensions are contemplated, hyper-dimensional k and r vectors, i.e. more than 3 dimensional, may exist and may be contemplated for some aspects. For the purposes of the disclosed technology, three dimensions suffice for proof of utility, and are contemplated without departing from the scope of the invention. [0057] FIG. 6 illustrates an example coordinate system with relevant array coordinate parameters used in a derivation section, according to some aspects of the disclosed technology. With reference to FIG 6, a linear array is contemplated for clarity and without departure from the scope of this invention. For a linear array of N elements (610), a coordinate frame (620) is selected such that the angle of incidence, q (630), of the electromagnetic wave-front vector (650) is denoted as 0 degrees, or 0 radians, when the vector (650) is parallel to the axis of the array (620); and is denoted as 90 degrees, or pi/2 radians, when the vector (650) is perpendicular to the axis of the array (620); and q (630) is denoted as 180 degrees, or pi radians, when the vector (650) is parallel to the axis of the array and is originating from, i.e. with the source, opposite the side of 0 degrees. The wave-front is depicted in 640 and is inherently perpendicular to the wave front vector (650). In this coordinate system, w n is contemplated, for clarification of the vector equation, as the complex exponential: Equation 9: [0058] Where q d is defined as the angle subtended between the steering vector (660) and the axis of the array (620). In this coordinate frame, the steering vector dot product, k × r n , can be represented by: Equation 10: [0059] Where q is the angle of the wave-front (640) resulting in the steering vector (660) in the same coordinate frame of the array contemplated above. Substituting Equation 9 and Equation 10 into Equation 8 yields: [0060] This summation is in the standard form whose closed form solution is given: [0061] Substituting the dummy variable Q for the complex exponential in Equation 12 yields a closed form solution for the AF expressed as:
[0062] Calculating the magnitude of the AF in Equation 13 and using the Euler identity for the complex representation of sine as shown below in Equation 14, simplifies the AF to the form shown in Equation 15:
q [0063] Equation 15 indicates that there are locations of minima and maxima within the array factor. These locations are periodic in nature as the sine function is periodic in nature. The maxima and minima occur when the denominator and numerator of Equation 15 are minimized, respectively. Equation 15 has maxima when the denominator approaches or is equal to 0. This occurs when the argument of the sine is an integer multiple of pi, and is described as:
[0064] Rearranging the argument of the sine, expanding the wave number, k, and solving for the [cosine] terms, the relationship described by Equation 16 is met when:
Equation 17: [0065] Similarly, Equation 15 has a minimum when the numerator is equal to zero while the denominator is non-zero. This is described as: [0066] Rearranging the argument of the sine, expanding the wave number, k, and solving for the [cosine] terms, the relationship described by Equation 17 is met when: [0067] Equations 17 and 19 show that the maxima and minima are proportional to the spacing d. Specifically, as“d” increases, the number of maxima and minima increase proportionally. [0068] FIG. 7 illustrates a relationship of an Array Factor (AF) and spacing of an element at 0.5l, 2l, and 3l. With reference to FIG. 7, the number of peaks is clearly shown to increase with d: 710 indicates the array factor with d = ½l; 720 represents the array factor with d = 2l; 730 represents the array factor for d = 3l. [0069] As described above, because the array system has two groups of elements, Group (a) and Group (b), the number of elements in Group (a) is represented by“Na” and the number of elements in Group (b) is represented by“Nb.” The spacing“d” between the elements of Group (a) is represented by“S a ” and the spacing between the elements of Group (b) is represented by “S b ”.
[0070] The resultant maxima of Group (a) and Group (b) can be derived from Equation 17 as:
[0071] The resultant minima of Group (a) and Group (b) can be derived from Equation 19 as:
[0072] The resultant AF of Group (a) can be expressed by substituting N a and S a into Equation 15 yielding: quation 4:
[0073] The resultant AF of Group (b) can be expressed by substituting N b and S b into Equation 15 yielding: [0074] To achieve the reduction factor, the array system is constructed with the spacing in Group (a) and/or Group (b) with S a and/or S b greater than ½l. [0075] It has been established that spacing in excess of ½l will result in conventionally undesirable grating lobes. With reference to FIG. 7, recall that 710 represents ½l spacing; 720 represents 2l spacing; and 730 represents 3l spacing. These undesired grating lobes can be seen at the callout 721, and at the callout 732. Curve 720 has 5 peaks with AF = 1 located at approximately 0, 1.05, 1.57, 2.09 and 3.14 radians. Furthermore, these undesired grating lobes can also be seen on curve 730. This curve has 7 peaks with AF = 1 located at approximately 0, 0.840, 1.23, 1.57, 1.91, 2.30, 3.13 radians. In contrast, 710 does not show any grating lobes and only contains one main lobe at approximately 1.57 radians. It is also evident from FIG. 7 that all element spacings synthesize a lobe at approximately 1.57 radians. This lobe is mathematically defined in Equation 17 when m = 0. It is also evident from FIG. 7 that all element spacing in excess of ½l synthesize multiple grating lobes. These lobes are mathematically defined in Equation 17 when m ¹ 0. [0076] It is also evident from FIG 7 that all element spacing contains minima, i.e. where AF = 0. In some aspects, with ½l spacing as illustrated by 710, these minima are located at approximately 0, 0.72, 1.05, 1.32, 1.82, 2.09, 2.42 and 3.14 radians. With a 2l spacing as illustrated by 720, these minima are located at approximately 0.36, 0.51, 0.62, 0.72, 0.81, 0.9, 0.97, 1.12, 1.19, 1.25, 1.32, 1.38, 1.45, 1.51, 1.63, 1.7, 1.76, 1.82, 1.89, 1.96, 2.02, 2.17, 2.25, 2.33, 2.42, 2.52, 2.64 and 2.79 radians. With a 3l spacing as illustrated by 730, these minima are located at approximately 0.29, 0.41, 0.51, 0.59, 0.66, 0.72, 0.78, 0.9, 0.95, 1, 1.05, 1.09, 1.14, 1.19, 1.27, 1.32, 1.36, 1.4, 1.45, 1.49, 1.53, 1.61, 1.65, 1.7, 1.74, 1.78, 1.82, 1.87, 1.96, 2, 2.05, 2.09, 2.14, 2.19, 2.25, 2.36, 2.42, 2.48, 2.56, 2.64, 2.73 and 2.85 radians. [0077] In one aspect of the subject technology, by constructing the array system with a specific relationship between S b , N a and S a , it is now possible to (1) synthesize the main lobe of Group (b) to be coincident or in the vicinity of the main lobe of Group (a), and (2) synthesize the undesired maxima (e.g., grating lobes) of Group (b) to be coincident or in the vicinity of the minima of Group (a). [0078] As described above with reference to Equation 3, Sb = Na*Sa. By substituting Equation 3 into the maxima equation for Group (b) defined in Equation 21, the location of the maxima of Group (b) may be identified:
[0079] Applying the cosine term of this calculation to the Array Factor for Group (a), defined in Equation 24, and expanding the wave number, k, we get the following relationship:
[0080] Cancelling like terms, the resulting form of the Group (a) Array Factor is:
[0081] Equation 28 shows that for all m where m ¹ 0, i.e. non-primary lobe, and m ¹ b*N a , where b is 1, 2, 3 . . . the numerator evaluates to 0 while the denominator is non-zero– thus indicating a minimum. Equation 28 also shows that for m = 0, and m = b*N a , where b is 1, 2, 3.. . the denominator evaluates to 0– thus indicating a maximum. Accordingly, it is shown that by constructing the array system with a specific relationship between S b , N a and S a , it is possible to (1) synthesize the main lobe of Group (b) to be coincident or in the vicinity of the main lobe of Group (a), and (2) synthesize the undesired maxima (e.g., grating lobes) of Group (b) to be coincident or in the vicinity of the minima of Group (a). [0082] Furthermore, it is clear that the maxima occurring at m = b*N a are subject to the constraints of Equation 21. Examining Equation 21, the left-hand side is limited in range between -1 and 1, when adjusted for steering angle. This imposes a constraint on the valid range for the right-hand side represented by:
[0083] Therefore, m must always satisfy the condition:
[0084] This constraint when applied to Equation 28 indicates that there will be a lobe at the main lobe where m =0, and there can only be as many grating lobes as permitted by Equation 30. For example, and in reference to FIG. 7, in 710, Sb = 0.5l ® -0.5 £ m £ 0.5. The only valid value for m is 0 therefore there can only be a main lobe. In 720, Sb = 2l ® -2 £ m £ 2, therefore m can assume the values -2, -1, 0, 1, and 2 thus there will be 5 lobes, 4 of which are undesired grating lobes (m¹0), and 1 of which is the main lobe (m=0) when Sb = 2l. Furthermore, in 730, Sb = 3l ® -3 £ m £ 3; therefore, m can assume the values -3, -2, -1, 0, 1, 2, and 3 indicating there will be 7 lobes, 6 of which are grating (m¹0), and 1 of which is the main (m=0). [0085] Equations 28, 29 and 30 establish the relationships which identify the empirical observations shown in FIG. 7 and described above. Beam Width Calculations: [0086] The half power beam-width of the array is determined when Equation 15 is equal to 1/Ö2 (i.e. -3dB) and solving for q d . Doubling this result yields the half power beam width angle of the array which is defined using Equation 2 as: Equation 30: q HPBW @ 0.89*l/L or q HPBW = 0.89/L’ [0087] FIG. 8 illustrates an example processor-based device that can be used to implement an active array system and/or a signal processing system, according to some aspects of the disclosed technology. FIG. 8 illustrates an example processing-based device 810. Device 810 includes a master central processing unit (CPU) 862, interfaces 868, and bus 815 (e.g., a PCI bus). When acting under the control of appropriate software or firmware, CPU 862 can be configured for performing operations for managing transmission of one or more transmit elements and/or the receipt and processing of reflected signals resulting from said transmission. CPU 862 preferably accomplishes all these functions under the control of software including an operating system and any appropriate applications software and/or firmware. CPU 862 can include one or more processors, or processing cores, 863 such as a processor from the Motorola family of microprocessors, or the ARM family of microprocessors and may be coupled with Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) such as Xilinx, Altera, Microsemi, and Lattice semiconductor, and digital signal processors (DSPs) such as those provided by various vendors such as TI and Analog Devices. In a specific embodiment, a memory 861 (such as non-volatile RAM and/or ROM) also forms part of CPU 862. However, there are many different ways in which memory can be coupled to device 810. [0088] Interfaces 868 can be interface cards (sometimes referred to as "line cards"). Among the interfaces, Ethernet interfaces, frame relay interfaces, cable interfaces, DSL interfaces, token ring interfaces, and the like are contemplated. However, other interfaces may be implemented, without departing from the scope of the technology. In addition, various high-speed interfaces may be provided such as fast token ring interfaces, wireless interfaces, Ethernet interfaces, Gigabit Ethernet interfaces, ATM interfaces, HSSI interfaces, POS interfaces, FDDI interfaces and the like. Generally, these interfaces may include ports appropriate for communication with the appropriate media. In some cases, they may also include an independent processor and, in some instances, volatile RAM. [0089] Although the system shown in FIG. 8 is one example of a processing-device that can be used to facilitate the implementation of various aspects of the disclosed invention, it is by no means the only device architecture on which the present invention can be implemented. Regardless of the device's configuration, it can employ one or more memories or memory modules (including memory 861) configured to store program instructions for the general- purpose network operations and mechanisms for roaming, route optimization and routing functions described herein. The program instructions may control the operation of an operating system and/or one or more applications, for example. [0090] It is understood that some of the described features and applications can be implemented as software processes that are specified as a set of instructions recorded on a computer-readable storage medium (also referred to as non-transitory computer-readable medium). When these instructions are executed by one or more processing unit(s) (e.g., one or more processors, cores of processors, or other processing units), they cause the processing unit(s) to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, RAM chips, hard drives, EPROMs, EEPROMS, flash memory, SD-Cards etc. The computer readable media does not include carrier waves and electronic signals passing wirelessly or over wired connections. [0091] In this specification, the term“software” includes firmware residing in read-only memory or applications stored in magnetic storage that can be read into memory for processing by a processor. Also, in some implementations, multiple software aspects of the subject disclosure can be implemented as sub-parts of a larger program while remaining distinct software aspects of the subject disclosure. In some implementations, multiple software aspects can also be implemented as separate programs. Finally, any combination of separate programs that together implement a software aspect described here is within the scope of the subject disclosure. In some implementations, the software programs, when installed to operate on one or more electronic systems, define one or more specific machine implementations that execute and perform the operations of the software programs. [0092] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be executed by a general-purpose processor, a digital signal processor, or describe a particular hardware configuration (such as VHDL and Verilog) to synthesize and execute the program on an ASIC, FPGA or other programmable hardware. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network. [0093] An array system of the subject technology may include various types of computer readable media and interfaces for various other types of computer readable media. One or more components of the platform may include a bus, processing unit(s), a system memory, a read-only memory (ROM), a permanent storage device, an input device interface, an output device interface that is configured to generate a graphical image. [0094] The bus may collectively represent all system, peripheral, and chipset buses that communicatively connect the numerous internal devices of the platform. For instance, the bus may communicatively connect processing unit(s) with ROM, system memory, and permanent storage device. [0095] From these various memory units, processing unit(s) retrieves instructions to execute and data to process in order to execute the processes of the subject disclosure. The processing unit(s) can be a single processor or a multi-core processor in different implementations. [0096] ROM stores static data and instructions that are needed by processing unit(s) and other modules of the array system. Permanent storage device, on the other hand, is a read-and-write memory device. This device is a non-volatile memory unit that stores instructions and data even when the platform is off. Some implementations of the subject disclosure use a mass-storage device (such as a magnetic or optical disk and its corresponding disk drive) as permanent storage device. [0097] Other implementations use a removable storage device (such as a floppy disk, flash drive, and its corresponding disk drive) as permanent storage device. Like permanent storage device, system memory is a read-and-write memory device. However, unlike storage device, system memory is a volatile read-and-write memory, such a random access memory. System memory stores some of the instructions and data that the processor needs at runtime. In some implementations, the processes of the subject disclosure are stored in system memory, permanent storage device, and/or ROM. For example, the various memory units include instructions for generating a graphical image, or processing data in accordance with some implementations. From these various memory units, processing unit(s) retrieves instructions to execute and data to process in order to execute the processes of some implementations. [0098] Bus also connects to input and output device interfaces and. Input device interface enables a user to communicate information and select commands to the array system. Input devices used with input device interface include, for example, alphanumeric keyboards and pointing devices (also called“cursor control devices”). Output device interfaces enables, for example, the display of images generated by the array system. Output devices used with output device interface include, for example, display devices, such as cathode ray tubes (CRT) or liquid crystal displays (LCD), specialized hardware such as heads up displays (HUDs), wearable display technologies, and other specialized display technologies. Some implementations include devices such as a touch screen that functions as both input and output devices. [0099] These functions described above can be implemented in digital electronic circuitry, in computer software, firmware or hardware. The techniques can be implemented using one or more computer program products. The processes and logic flows can be performed by one or more programmable processors and by one or more programmable logic circuitry. General and special purpose computing devices and storage devices can be interconnected through communication networks. [00100] Some implementations include electronic components, such as microprocessors, storage and memory that store computer program instructions in a machine-readable or computer-readable medium (alternatively referred to as computer-readable storage media, machine-readable media, or machine-readable storage media). Some examples of such computer- readable media include RAM, ROM, read-only compact discs (CD-ROM), recordable compact discs (CD-R), rewritable compact discs (CD-RW), read-only digital versatile discs (e.g., DVD- ROM, dual-layer DVD-ROM), a variety of recordable/rewritable DVDs (e.g., DVD-RAM, DVD-RW, DVD+RW, etc.), flash memory (e.g., SD cards, mini-SD cards, micro-SD cards, etc.), magnetic and/or solid state hard drives, read-only and recordable discs, ultra-density optical discs, any other optical or magnetic media, and floppy disks. The computer-readable media can store a computer program that is executable by at least one processing unit and includes sets of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as is produced by a compiler, and files including higher-level code that are executed by a computer, an electronic component, or a microprocessor using an interpreter. [00101] While the above discussion primarily refers to microprocessor or multi-core processors that execute software, some implementations are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In some implementations, such integrated circuits execute instructions that are stored on the circuit itself. [00102] As used in this specification and any claims of this application, the terms“computer”, “server”,“processor”, and“memory” all refer to electronic or other technological devices. These terms exclude people or groups of people. As used in this specification and any claims of this application, the terms“computer readable medium” and“computer readable media” are entirely restricted to tangible, physical objects that store information in a form that is readable by a computer. These terms exclude any wireless signals, wired download signals, and any other ephemeral signals. [00103] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, or any combination of one or more such back end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), an inter-network (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks). [00104] It is understood that any specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged, or that all illustrated steps be performed. Some of the steps may be performed simultaneously. For example, in certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. [00105] The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean“one and only one” unless specifically so stated, but rather“one or more.” Unless specifically stated otherwise, the term“some” refers to one or more. Pronouns in the masculine (e.g., his) include the feminine and neuter gender (e.g., her and its) and vice versa. Headings and subheadings, if any, are used for convenience only and do not limit the subject disclosure. [00106] A phrase such as an“aspect” does not imply that such aspect is essential to the subject technology or that such aspect applies to all configurations of the subject technology. A disclosure relating to an aspect may apply to all configurations, or one or more configurations. A phrase such as an aspect may refer to one or more aspects and vice versa. A phrase such as a “configuration” does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. A disclosure relating to a configuration may apply to all configurations, or one or more configurations. A phrase such as a configuration may refer to one or more configurations and vice versa. [00107] The word“exemplary” or“example” is used herein to mean“serving as an example or illustration.” Any aspect or design described herein as“exemplary” or“example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. [00108] Furthermore, to the extent that the term“include,”“have,” or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term “comprise” as“comprise” is interpreted when employed as a transitional word in a claim. [00109] A reference to an element in the singular is not intended to mean“one and only one” unless specifically stated, but rather“one or more.” The term“some” refers to one or more. All structural and functional equivalents to the elements of the various configurations described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the subject technology. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the above description. Definition of Terms: [00110] l: Wavelength [00111] q: Far field location angle [00112] q d : Steering direction [00113] q HPBW : Spatial resolution of an array system [00114] AF: Array Factor is the field transmission or reception pattern that occurs (independent of wavelength) when combining sources or receivers in a coherent process. [00115] AI: Artificial Intelligence [00116] w n : Complex excitation coefficients [00117] d: Spacing between elements [00118] k: Wave number vector [00119] k: Wave number [00120] L: Aperture length [00121] M: Complexity Reduction Factor [00122] Mtx: Complexity Reduction Factor for transmit group [00123] Mrx: Complexity Reduction Factor for receive group
[00124] N: Element number
[00125] Na: Number of elements in group A (transmitter)
[00126] Nb: Number of elements in Group B (receiver)
[00127] Nc: Number of elements in a conventional array design
[00128] Nac: Number of elements in group A (transmitter) of a conventional array
[00129] Nbc: Number of elements in Group B (receiver) of a conventional array
[00130] : Direction unit vector [00131] : Location vector of the elements
[00132] Sa: Inter-element spacing in Group A (transmitter)
[00133] Sb: Inter-element spacing in Group B (receiver)