Title:
ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE AND TOUCH PANEL DISPLAY DEVICE COMPRISING SAME
Document Type and Number:
WIPO Patent Application WO/2017/213178
Kind Code:
A1
Abstract:
Provided are an active matrix substrate capable of reducing the difference in parasitic capacitance between lead-out lines connected to signal lines, and a display device and touch panel display device comprising same. The active matrix substrate comprises a plurality of signal lines S1-S9 arranged so as to be parallel to each other in a display region provided on the substrate, and a plurality of lead-out lines L1-L9 that are connected to the plurality of signal lines S1-S9 outside the display region. Outside the display region, the plurality of lead-out lines L1-L9 are arranged in at least three layers comprising a lowermost wiring layer formed at a position that is the closest to the substrate, an uppermost wiring layer formed at a position that is the furthest from the substrate, and an intermediate wiring layer formed between the lowermost wiring layer and the uppermost wiring layer. Capacitance is formed between a signal line S3 connected to a lead-out line L3 provided in the lowermost wiring layer and a signal line S4 connected to a lead-out line S4 provided in the uppermost wiring layer.
Inventors:
TOMINAGA MASAKATSU
YOSHIDA MASAHIRO
HARA YOSHIHITO
OGASAWARA ISAO
MIMURA YASUHIRO
YOSHIDA MASAHIRO
HARA YOSHIHITO
OGASAWARA ISAO
MIMURA YASUHIRO
Application Number:
PCT/JP2017/021159
Publication Date:
December 14, 2017
Filing Date:
June 07, 2017
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G09F9/30; G02F1/1333; G02F1/1345; G02F1/1368; H01L29/786; H01L51/50
Domestic Patent References:
WO2013021866A1 | 2013-02-14 |
Foreign References:
JP2012032799A | 2012-02-16 | |||
JP2013122752A | 2013-06-20 | |||
JP2006220832A | 2006-08-24 | |||
JP2015004910A | 2015-01-08 | |||
JP2007041346A | 2007-02-15 | |||
JPH10268348A | 1998-10-09 | |||
US20140168591A1 | 2014-06-19 |
Attorney, Agent or Firm:
KAWAKAMI Keiko et al. (JP)
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