Title:
ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/225690
Kind Code:
A1
Abstract:
An active-matrix substrate according to an embodiment of the present invention is provided with a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT has: a lower gate electrode provided on the substrate; a gate insulating layer covering the lower gate electrode; an oxide semiconductor layer arranged on the gate insulating layer; a source electrode in contact with the source contact region of the oxide semiconductor layer; a drain electrode in contact with the drain contact region of the oxide semiconductor layer; an insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and an upper gate electrode provided on the insulating layer. When seen from the normal direction of the substrate, the upper gate electrode does not overlap a first electrode that is one of the source electrode and the drain electrode, and a second electrode that is the other of the source electrode and the drain electrode does not overlap the lower gate electrode.
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Inventors:
TAKEDA YUJIRO
MATSUKIZONO HIROSHI
ODA AKIHIRO
MURASHIGE SHOGO
TANAKA KOHHEI
MATSUKIZONO HIROSHI
ODA AKIHIRO
MURASHIGE SHOGO
TANAKA KOHHEI
Application Number:
PCT/JP2018/021389
Publication Date:
December 13, 2018
Filing Date:
June 04, 2018
Export Citation:
Assignee:
SHARP KK (JP)
International Classes:
G09F9/30; G02F1/1368; H01L21/336; H01L21/8234; H01L27/088; H01L29/786
Foreign References:
| JP2015233161A | 2015-12-24 | |||
| JP2011172217A | 2011-09-01 | |||
| US20070290227A1 | 2007-12-20 | |||
| JP2011205103A | 2011-10-13 | |||
| JP2002064208A | 2002-02-28 |
Attorney, Agent or Firm:
OKUDA Seiji (JP)
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