Title:
AD CONVERTER
Document Type and Number:
WIPO Patent Application WO/2014/141350
Kind Code:
A1
Abstract:
The present invention is provided with the following: a delta sigma AD converter (2) that receives an analog signal from an input terminal (1) and thereby obtains higher-order bit conversion results; a first cyclic-type AD converter (6) to which a residual signal from which higher-order bits are removed is imparted, and that carries out conversion processing with an amplification factor of one and obtains 1.5 bit conversion results; a second cyclic-type AD converter (8) that carries out conversion processing with an amplification factor of two and obtains lower-order bit conversion results; and a shift register (3) and digital accumulator circuit (4) to which the conversion results of higher-order bits, 1.5 bits, and lower-order bits are imparted so that an AD conversion value is output therefrom.
More Like This:
| JP4226082 | How to detect a segment |
| JPH0677828 | SERIAL PARALLEL TYPE A/D CONVERTER |
| JPS60148228 | ANALOG-DIGITAL CONVERTER |
Inventors:
GOTO YOSUKE
YAMADA MICHIKO
YAMADA MICHIKO
Application Number:
PCT/JP2013/007655
Publication Date:
September 18, 2014
Filing Date:
December 26, 2013
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H03M1/14
Foreign References:
| JP2007036580A | 2007-02-08 | |||
| JP2002532937A | 2002-10-02 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Download PDF: