CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit under 35 U.S.C. § 1 19 (e) to United States

Provisional Application Number 62/010,062 entitled ADAPTABLE INPUT/OUTPUT APPARATUS AND METHOD, filed June 10, 2014, the content of which is incorporated herein by reference in its entirety.

Background of the Invention

Field of the Invention

[0002] The subject matter disclosed herein generally relates to a programmable integrated circuit that configures an input module to accept a variety of different input voltages and currents for use with user inputs.

Brief Description of the Related Art

[0003] A variety of approaches have been used in the creation of input/output (I/O) devices, including the use of numerous I/O modules based on the power source incorporated in the system. For example, separate I/O modules may be necessary to accommodate a wide range of power sources as well as currents.

[0004] In some circumstances, individual modules may be required for various voltage ranges. For example, DC voltages ranging between 5 and 250 volts, AC voltages of 120 or 240 volts, as well as different current draws may be utilized in different circumstances. The required I/O modules are often costly due to the number of different modules and require an increase in manufacturing time due to the specificity involved in their production. Further, it may be difficult to select a correct module based on individual needs due to the large number of modules to choose from.

[0005] The above-mentioned problems have resulted in some user dissatisfaction with previous approaches.

Brief Description of the Invention

[0006] The approaches described herein provide a programmable integrated circuit which assists in configuring an input module so as to allow the input module to accept and/or process a variety of input voltages and currents to be provided to user inputs. In one aspect, the integrated circuit and the input module are coupled between the user inputs and a backplane. The backplane may be coupled to a control system. The use of the adaptable integrated circuit advantageously allows the replacement of dedicated hard wired circuit boards that otherwise may be required.

[0007] So configured, the I/O module described herein may be shared across a number of input voltages and/or currents, thus reducing product catalogs and their associated costs.

Advantageously, the I/O module may be used with both AC and DC power sources, and may be incorporated in systems with different numbers of channels. Further, the I/O module may sense voltages for detecting open wiring or sense over-application of voltage for fault detection.

[0008] In some approaches, an adaptable input-output (I/O) apparatus used within a channel that supplies power to a user system is provided and includes an input decision module, a power control module, and an interface module coupled to the input decision module and the power control module. The interface module is configured to receive at least one preprogrammed threshold. The input decision module is configured to monitor and average an input voltage of the user system, periodically compare the average voltage to the preprogrammed threshold, and, based on the comparison, determine an adjustment to the power control module. This adjustment is effective to cause the power control module to maintain a power dissipation of the channel to be within a safe operating range.

[0009] In some forms, the input decision module may include a voltage controlled oscillator (VCO) and a frequency counter to provide an average value of measured voltage over time. In other examples, the input decision module may include an analog-to-digital converter and averaging logic that is configured to average any number of recent samples.

[0010] In some approaches, the power control module is configured to adjust the amount of current being drawn by the user system. This adjustment may be performed to maintain a present power dissipation amount of the channel. The apparatus may further transmit an alert upon exceeding the preprogrammed threshold which may alert a user of the presence of an anomaly. The apparatus may further be configured to stop transmitting power to the user system.

[0011] In many of these examples, the input decision module may include a

microcontroller having analog interfaces that are capable of accepting analog or digital inputs. The input decision module may comprise an application specific integrated circuit (ASIC).

Brief Description of the Drawings

[0012] For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawings wherein:

[0013] FIG. 1 comprises a block diagram illustrating an exemplary I/O system according to various embodiments of the present invention; [0014] FIG. 2 comprises a block diagram illustrating an exemplary input channel according to various embodiments of the present invention;

[0015] FIG. 3 comprises a block diagram illustrating an exemplary application-specific integrated circuit (ASIC) which may be utilized in the I/O system of FIG. 1 according to various embodiments of the present invention;

[0016] FIG. 4 comprises a circuit diagram illustrating an exemplary rectifier circuit of the

ASIC of FIG. 3 according to various embodiments of the present invention;

[0017] FIG. 5 comprises a circuit diagram illustrating an exemplary voltage-controlled oscillator (VCO) of the ASIC of FIG. 3 according to various embodiments of the present invention;

[0018] FIG. 6 comprises a circuit diagram illustrating an exemplary current sink of the

ASIC of FIG. 3 according to various embodiments of the present invention;

[0019] FIG. 7 comprises a flow chart illustrating exemplary decision logic of an I/O system according to various embodiments of the present invention;

[0020] FIG. 8 comprises a circuit diagram illustrating connections to a user system in accordance with various embodiments of the present invention.

[0021] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity. It will further be appreciated that certain actions and/or steps may be described or depicted in a particular order of occurrence while those skilled in the art will understand that such specificity with respect to sequence is not actually required. It will also be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein.

Detailed Description of the Invention

[0022] Approaches are provided that overcome the need for large numbers of different

Input/Output (I/O) modules to implement desired I/O architectures. In one aspect, universal I/O architecture using Application Specific Integrated Circuits (ASICs) allow for the direct replacement of existing I/O modules. By utilizing the present approaches, the I/O module may be programmed to accept a number of currents and/or voltages previously provided with the dedicated modules and will function similarly to these replaced modules.

[0023] In one specific example, a programmable integrated circuit is provided that helps to configure or adapt an input module so as to allow the input module to accept and/or process a variety of different input voltages provided to user inputs. The circuitry, coupled to the integrated circuit, further allows for variations to the electrical load present at the user inputs such that the input currents may be adjusted to allow for power dissipation limits across a wide range of potential voltages. The integrated circuit and the input module are, in one aspect, coupled between the user inputs and a backplane. The backplane may be coupled to a control system. The use of the adaptable integrated circuit advantageously allows the replacement of dedicated hardwired circuit boards that otherwise would be required.

[0024] Referring now to FIG. 1, one example of an I/O system 100 is described. The I/O system 100 includes a backplane 102, an isolated power supply 104, a complex programmable logic device (CPLD) 106, LED indicators 108, global settings interface 110, connections 114 from the backplane 102 to the CPLD 106, an isolation barrier (or digital isolator) 116, connections 118 from the CPLD 106 to the digital isolator 116, an ASIC 140, and connections 120 from ASIC 140 to a user system.

[0025] The backplane 102 or logic controller allows the I/O system 100 to connect to a control system (not shown). The backplane 102 receives power from the isolated power supply 104 via power and ground connections. The backplane 102 is communicatively coupled to the CPLD 106 through connections 1 14, which may include a select line, a clock line, a master out serial line, and a master in serial line connections. Other connections may also be provided.

[0026] Isolated power supply 104 may include a low drop-out circuit and a driver for isolated power. In some aspects, the low drop-out circuit includes a voltage regulator as well as a transformer. In one example, the backplane 102 provides power to the isolated supply. In other examples, connections 120 to the user system provide power to the isolated power supply.

[0027] The CPLD 106 includes LED indicators 108 which indicate operating conditions of portions of the I/O system 100. For example, the LED indicators 108 may signify when particular switches are opened, closed, or working properly.

[0028] Global settings interface 1 10 is a calibration interface that allows the CPLD to operate according to desired software characteristics. The software characteristics may include, for example, desired power and current values to be seen by the user system. In one aspect, this information includes calibration information of an individual ASIC 140 for each channel being used. Because each ASIC 140 may have varying voltage requirements, this information is uploaded into settings 110 and subsequently to CPLD 106. CPLD 106 also includes local storage memory which allows desired operational settings to be stored directly thereto. In this configuration, CPLD 106 provides ASIC 140 with the appropriate calibration information. The isolation barrier 116 protects transmissions between ASIC 140 and CPLD 106. In some examples, connections 1 18 include communications from isolation barrier 116 to CPLD 106 occur via a serial peripheral interface including a select line, clock line, and other components. Accordingly, data may flow in both directions between isolation barrier 1 16 and CPLD 106 using connections 118.

[0029] In one aspect, the ASIC 140 is a replacement for a portion of previous I/O systems and allows the I/O system 100 described herein to accept different current and voltage ranges originating from isolated power supply 104. In these regards, ASIC 140 is configured to support a number of input channels depending on the user system requirements. ASIC 140 includes connections for coupling to a user desired system. ASIC 140 will be described in further detail below.

[0030] In operation, upon the backplane 102 receiving power from the isolated power supply 104, initial settings 1 10 are sent to CPLD 106. These settings 1 10 correspond to the required input voltage and/or current necessary to operate the desired user system. At this time, the I/O system 100 will "learn" the type of design or configuration it represents (for example, a 24vdc, 120 vac, or other voltage design) and accordingly, will be able to accept user inputs appropriate for the desired design or configuration. The backplane 102 then configures appropriate thresholds and registers in ASIC 140. These thresholds and registers designate the amount of current each channel of the ASIC 140 should draw at startup as well as designate long- term current usage. The ASIC 140 then regulates the power and/or current at user inputs based on this configuration. After the initial calibration of the I/O system 100, settings 110 will provide normal operating information to the CPLD 106 and to the registers contained within ASIC 140. Thus, the threshold values may either be sent from settings 110 or the CPLD 106 to ASIC 140. If a manufacturer wishes to provide a user with the ability to provide different settings to the user system, the I/O system 100 will be configured to accept settings 110. Alternatively, a

manufacturer may provide pre-configured settings to the CPLD 106, thus restricting future modifications. Further, it is understood that in some examples, the thresholds and registers may designate different input variables received by the user system.

[0031] Referring now to FIG. 2, an example of an input channel 200 is provided. Input channel 200 includes connections 202 to the isolation barrier 116 and backplane interface previously described, ASIC 204, input decision module 206, power control circuit 208, communications interface 210, and wiring 212 and 214.

[0032] Input decision module 206 receives inputs from the user system and monitors its operation. Input decision module 206 further is used to determine the voltage seen at a terminal block (not shown). Input decision module 206 connects to the user system via wiring 212. Power control circuit 208 regulates the amount of power sent to the user system. Power control circuit 208 connects to field power via wiring 214. Input decision module 206 and power control circuit 208 are operatively coupled to each other by communications interface 210. The communications interface 210 also communicates via connections 202 to the isolation barrier and backplane interface.

[0033] In operation and in one example, I/O system 100 includes groups of eight, 16, 36 or more input channels 200 which may be connected to different individual user systems sharing the same common reference or system ground. These user systems may require different voltages and currents at their inputs in order to properly operate and the ASIC configures the I/O system to operate at these different currents and voltages. Accordingly, I/O system 100 regulates the currents and voltages seen at the input of each user system depending upon the needs of the user system. In some examples, I/O system 100 may be used with point isolated systems where each channel is individually isolated to allow for floating input connections. This may allow for connections within a user system at different voltage levels and/or grounding systems.

[0034] Referring now to FIG. 3, an example of ASIC 300 is herein described. ASIC 300 includes a rectifier circuit 302, input wiring 304, a voltage-controlled oscillator (VCO) 306, wiring 308, a frequency counter 310, an interface 312, threshold decision logic 314, a DSM driver for sink current 316, and sink control wiring 318.

[0035] The rectifier circuit 302 functions as a full wave rectifier which converts a current to a voltage. The rectifier circuit 302 includes a plurality of resistors, capacitors, and diodes which convert a first waveform into a second waveform. By using diodes to route currents based on voltage polarity combined with an operational amplifier, the circuit may be used to obtain the rectified value or signal magnitude.

[0036] The rectifier circuit 302 connects to a user system via input wiring 304, which may include a high impedance resistor which reduces the voltage seen by and protects the ASIC 300 against power surges. In some examples, the rectifier circuit 302 allows each input to be referenced to a common floating ground.

[0037] VCO 306 is driven by rectifier circuit 302, which ensures the VCO receives a positive voltage. Wiring 308 is also provided to VCO 306 which includes a timing capacitor to configure desired frequency to measure. VCO 306 converts an input voltage to oscillations in order to generate an output frequency. [0038] The frequency counter 310 measures the frequency generated by VCO 306 and transmits this value to interface 312 and threshold decision logic 314.

[0039] The interface 312 couples the ASIC 300 to the isolation barrier externally.

Additionally, interface 312 couples the frequency counter 310 and threshold decision logic 314 thereto for communication with the isolation barrier. In some examples, interface 312 transmits data including toggle flags which confirm there is a working connection, a counter overflow flag for indicating if any of the counters overflow prior to being automatically read (which would indicate improper functionality), an over-temperature flag if the I/O system 100 exceeds a specific temperature, and other information.

[0040] The threshold decision logic 314 compares the frequency received to values determined by the logic device for all of the channels in I/O system 100. The threshold decision logic 314 outputs two different settings to the DSM driver for sink current 316 based on established thresholds obtained either directly from settings or values stored in in the local configuration memory of the CPLD. The threshold decision logic 314 is discussed in further detail below with reference to Fig. 7.

[0041] In one example, elements 302, 306, 310, and 314 are provided as an

implementation of the input decision module 206 of FIG. 2. Further, elements 312 and 316 may be provided as an implementation of the communications interface 210 and power control circuit 208, respectively, of FIG. 2.

[0042] The DSM driver for sink current 316 sends a signal having a duty cycle that is varied based on high frequency signals such that the instantaneous average of binary matches a desired signal. Thus, the DSM driver for sink current 316 sends the desired signal to the user system using sink control wiring 318, thus allowing proper power and current values to be seen at the input of the user system.

[0043] In some examples, the VCO 306 and frequency counter 310 may be combined into a voltage measurement component or device. In these examples, the voltage measurement may include an analog-to-digital (A-D) converter used to obtain a value of bits representing what the instantaneous rectifier output is as opposed to using a frequency counter providing an average of the rectifier circuit voltage. As such, an averaging logic may be implemented using multiple values of the A-D input. In some examples, the eight most recent samples may be used to obtain the average. Other examples are possible.

[0044] Referring now to FIG. 4, one example of a rectifier circuit 400 is described. The rectifier circuit 400 includes a first resistor 402, a second resistor 404, a third resistor 406, a fourth resistor 408, an operational amplifier (op-amp) 410, a first diode 412, and a second diode 414.

[0045] The purpose of the rectifier circuit 400 is to change the waveform from AC to DC.

This is accomplished as follows: A current/voltage waveform is received at an input at "ΡΓΝ_ΓΝ" when positive will be coupled via second diode 414 to the first resistor 402 connected to ground. The voltage at the non-inverting input of the operational amplifier 410 is thus a combination of currents from "ΡΓΝ_ΓΝ" and "DVDD" via second resistor 404. The operational amplifier 410 inverting input will only sense the output "RECTIFIER" because the polarity on first diode 412 blocks any current flow through the parallel resistors 406 and 408. When the "PIN IN" polarity is negative, resistor 402 blocks any current flow while the current flows through resistor 404. This modifies the operation from a buffer to an inverting amplifier resulting in "RECTIFIER" being the magnitude of "PIN IN." Resistors 402 and 404 provide a slight offset such that signal "RECTIFIER" is above a level sufficient for the following section of VCO 306 to operate.

[0046] Referring now to FIG. 5, one example of a voltage controlled oscillator (VCO)

500 is described. The VCO 500 includes a comparator or op amp 502, a first resistor 504, a second resistor 506, a third resistor 508, a fourth resistor 510, a fifth resistor 512, a sixth resistor 514, a seventh resistor 516, an eighth resistor 518, a diode 520, and a capacitor 522. The VCO 500 is used to convert an input voltage to oscillations in order to generate an output frequency. In operation, the "RECTIFIER" signal provides a current via resistor 518 into capacitor 522. A second path to capacitor 522 is provided by the connections to diode 520 and resistor 16, both of which are controlled by connections to the comparator 502 output. Comparator 502, combined with resistors 504, 508, and 512, senses the voltage at capacitor 522 via resistor 510, with the comparator output being an open collector or drain to ground. When the capacitor voltage is below a threshold set by the values of "DVDD" and resistors 504, 508, and 512, the comparator output will be a high resistance to ground. This allows for current via resistors 506 and 516 along with input current via resistor 18 to charge the capacitor 522, which raises its voltage. Once the capacitor voltage exceeds a threshold, the comparator will change output states to a low impedance to ground. This causes the capacitor 522 to be discharged via diode 520 and resistor 514 dropping the voltage until the comparator 02 senses that the voltage is below a threshold to cause the comparator output to again go to a high resistance state. This cycle repeats, with the variation in frequency being related to the change in time to charge the capacitor due to the input voltage "RECTIFIER."

[0047] Referring now to FIG. 6, one example of a current sink circuit 600 is described.

The current sink circuit 600 includes a diode 602, a transistor 604, a capacitor 608, and a resistor 610. In operation, a binary bit stream at "PIN_SINK" is filtered by resistor 610 and capacitor 608 acting as a low pass filter. This serves to set the base of transistor 604 at the average value of the bit stream, which is a delta sigma modulated pattern forcing the binary average to be under logic control. With the base voltage set for transistor 604 (or gate voltage if a field effect transistor were used), the emitter voltage is one diode drop less. Thus, the current flowing through resistor 606 is the base voltage minus a diode drop then divided by the resistance. For a transistor, the current at the emitter is the collector current plus the base current, or essentially the same for transistor current gains of 50 or higher. This allows for the choice of the binary bit stream average value to directly control a preset current flowing through transistor 604 and diode 602. To avoid negative current flow from damaging the circuitry, diode 602 is in series with the current sink. When the user system is set for alternating current (AC) voltages, the binary stream is set continuously low, thus forcing the transistor 604 to remain off with no current flow.

[0048] A person having skill in the art will appreciate that the circuits contained herein are merely exemplary and may be modified as required. Further, these elements may be any combination of hardware and software components, for example, discrete components, microprocessors, ASICs, computer software, or any combination thereof.

[0049] Turning to Fig. 7, a decision logic process 700 is herein described. The decision logic process 700 provides instructions to operate the DSM driver previously described based on whether input signals fall within threshold values derived from either the settings or the CPLD as previously described. The decision logic process 700 sends a first setting to the DSM driver upon reaching a first threshold value. If the input signals do fall within the threshold value for a long enough time, the decision logic process 700 sends a second setting to the DSM driver.

Accordingly decision logic process 700 effects the transmission of a larger current to the user system when the switch initially closes (when the first setting is sent to the DSM driver), followed by a smaller current when operating power is reached (when the second setting is sent to the DSM driver).

[0050] The process utilizes certain flags, variables, and other programming entities. In these regards, a "busy" flag represents when the input system results are being decided to avoid reading information as it may be changing. An overflow flag represents where a counter may have too large a value indicating either too long a time between reads or too high an input frequency from the VCO. The frequency count represents a value related to the input voltage into the channel's VCO.

[0051] First, at step 702, the system powers up. Next, at step 704, the process 700 waits for registry transfers coming from the control side of the interface in an isolation buffer. At this step, the process 700 is being configured with threshold values which correspond to the desired power and current levels to be seen at the input of the user system. At step 706, upon recent commands being received with the final register being loaded, the register map will indicate the timer is a high value (as opposed to 0) and will proceed to step 708.

[0052] At step 708, the timing interval is initiated. Here, the timer begins to time and all counters begin to count. The busy flag is turned off so values at step 708 can be read. At step 710, the process 700 determines whether the timer reads a value greater than 90%. When the timer does read a value greater than 90%, the process 700 proceeds to step 712. The concept of 90% is controlled by timer values loaded during step 704, where the ratio of time that the VCO operates to the time between reads may typically be set at 80 to 99% depending on how quickly the threshold decision logic will operate compared to the time it takes to have counters reach their maximum value.

[0053] At step 712, the busy flag is turned on and all counters are frozen. Additionally, channel holding registers are loaded with the counter values and any overflow flags are cleared by process 700. Next, at step 714, the process 700 performs the following steps for each channel. At step 716, process 700 determines whether the holding register for the given channel is above or below a lower threshold. If the channel hold (i.e., the value or values from the frequency counter) is below a threshold, process 700 proceeds to step 718, where the channel switch is designated as open indicating the channel as off. Further, at step 718, values are set such that the channel provides a higher current level when the switch is closed, and the pulse counter for this channel is cleared. The process 700 then proceeds to step 732.

[0054] If, at step 716, the channel hold is above a threshold (indicating the switch is on due to the availability of a voltage), process 700 proceeds to step 720. At step 720, the frequency count generated is established by process 700.

[0055] At step 722, process 700 determines whether the frequency count is above the higher threshold. If the frequency count is above the higher threshold, process 700 proceeds to step 724. If the frequency count is below the higher threshold, process 700 proceeds to step 726.

[0056] At step 724, current is quickly shut off and a range flag is sent to a DSM pulse counter designating a maximum value. This is meant to protect against too high an input voltage causing too high a power dissipation in the circuit. Process 700 then proceeds to step 732.

[0057] At step 726, the pulse counter increases incrementally. This pulse counter counts the number of times flowing through a specified channel for the purpose of determining the duration of the pulse. At step 728, the pulse counter is compared to a preset pulse duration. If the pulse is greater than the duration, the operating current is set to the value for "DSM_LOW" to reduce input power consumption, otherwise the process 700 proceeds to step 732. The steps 720 to 730 allow for the input current to the channel to be programmed. For DC inputs with an initial higher current level dropping to a low level after a programmed time, "DSM_LOW" is less than "DSM HIGH." If the channel is configured for AC inputs, both "DSM LOW" and

"DSM HIGH" are set to zero. If the channel is for DC with a steady current, then "DSM LOW" equals "DSM HIGH."

[0058] At step 732, process 700 determines if there are more channels. If so, process 700 returns to step 714. If there are no more channels, process 700 proceeds to step 734, where it is determined whether the timer has exceeded a maximum value. When the time has exceeded the maximum value, process 700 returns to step 708.

[0059] In some examples, each channel may be provided with different power and current levels. Accordingly, process 700 loads these different values upon powering up and uses these threshold values during execution.

[0060] It is understood that in examples utilizing a single voltage measurement component as previously described, the process 700 must receive the readings from the frequency counter over a duration of time. This serves to provide an average of the readings, such as when the most recent eight timer passes are used to acquire eight sets of channel readings. The channel hold becomes the value of adding the most recent eight readings for a channel and shifting three bits to the right to divide by eight. This may be performed as part of a modified read in block 712.

[0061] Turning to FIG. 8, a circuit diagram 800 illustrating connections from the ASIC to a user system is provided. The circuit diagram 800 includes a positive input terminal 802, a negative input terminal 804, a first resistor 806, a first capacitor 808, a diode 810, a transistor 812, a second resistor 814, a third resistor 816, a second capacitor 818, a fourth resistor 820, and a third capacitor 822.

[0062] The positive 802 and negative 804 input terminals are used to connect the user system to the desired channel of the input module. The DSM or sink control previously described outputs to transistor 812. Transistor 812 may be a FET or bipolar transistor. The drain (or collector if using a bipolar transistor) of transistor 812 is connected to the input terminal 804 through diode 810. The source (or emitter if using a bipolar transistor) of transistor 812 is connected to the second resistor 814 that connects to group common. The sink control wiring is connected to the fourth resistor 820, which connects to the base of transistor 812. The first resistor 806, first capacitor 808, and the diode 810 and second resistor 814 are in parallel branches spanning between input terminals 802, 804.

[0063] In operation, the DSM driver sends a current through the sink control wiring to transistor 812. If the user system is configured to receive an AC input, transistor 812 is turned off entirely to prevent unequal currents on positive and negative portions of the cycle. Conversely, when the user system is configured to receive a DC input, transistor 812 sends varying amounts of current to the user system. Based on the current level, transistor 812 will serve as a current sink at a programmable level(s) of current.

[0064] It will be understood that the functionality of the ASIC may be provided on a single, physical chip or on multiple chips (or other components) disposed at multiple locations. For example, certain components of the ASIC may be disposed on either side of the isolation barrier. In one approach, the ASIC may only include the rectifier circuit and the VCO, as the other components of the ASIC may already be on an existing input module. In other words, the system described herein may be retrofitted on an existing input module without the need for substantial system redesign.

[0065] It will be appreciated by those skilled in the art that modifications to the foregoing embodiments may be made in various aspects. Other variations clearly would also work, and are within the scope and spirit of the invention. The present invention is set forth with particularity in the appended claims. It is deemed that the spirit and scope of that invention encompasses such modifications and alterations to the embodiments herein as would be apparent to one of ordinary skill in the art and familiar with the teachings of the present application.