MEASUREMENT

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63/171,622, filed April 7, 2021, entitled “Adaptive Frequency Scaling Based On Clock Cycle Time Measurement.”

FIELD OF THE INVENTION

[0002] The invention relates to the field of integrated circuits.

BACKGROUND

[0003] Integrated circuits (ICs) may include analog and digital electronic circuits on a flat semiconductor substrate, such as a silicon wafer. Microscopic transistors are printed onto the substrate using photolithography techniques to produce complex circuits of billions of transistors in a very small area, making modem electronic circuit design using ICs both low cost and high performance. ICs are produced in assembly lines of factories, termed foundries, which have commoditized the production of ICs, such as complementary metal-oxide-semiconductor (CMOS) ICs. Digital ICs contain billions of transistors arranged in functional and/or logical units on the wafer, and are packaged in a metal, plastic, glass, or ceramic casing. The casing, or package, is connected to a circuit board, such as by using solder. Types of packages may include a leadframe (though- hole, surface mount, chip-carrier, and/or the like), pin grid array, chip scale package, ball grid array, and/or the like, to connect between the IC pads and the circuit board. As used herein, the term IC means the integrated circuit including the package.

[0004] Semiconductor ICs use synchronous digital logic, controlled by a clock signal. The clock signal is generated on the Semiconductor IC. Various factors can lead to the clock frequency changing. Adaptive Frequency Scaling (AFS) is known for control of the clock frequency. Controlling AFS operation is desirable for optimal performance of the semiconductor IC.

[0005] The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the figures. SUMMARY

[0006] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods, which are meant to be exemplary and illustrative, not limiting in scope.

[0007] In an embodiment, there is provided a controller for generation of a clock signal in a semiconductor integrated circuit (IC), the controller comprising: a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal; and an Adaptive Frequency Scaling (AFS) circuit, configured selectively to adjust a frequency of the clock signal based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

[0008] In embodiments, the AFS circuit is configured to activate adjusting a frequency of the clock signal if the output of the NMA descends below a first threshold. In embodiments, the AFS circuit is configured to deactivate adjusting a frequency of the clock signal if the output of the NMA rises above a second threshold, the second threshold being higher than the first threshold.

[0009] In embodiments, the AFS circuit is configured, when activated, to reduce the frequency of the clock signal in response to the output of the NMA indicating a reduction in the effective cycle time of the clock signal.

[0010] In embodiments, the NMA comprises: a time-to-digital converter, arranged to output a measurement of a cycle time of an input clock signal, the parameter indicative of an effective cycle time of the clock signal being based on the measurement output of the time-to-digital converter. In embodiments, the time-to-digital converter comprises a tapped delay line. In embodiments, the NMA further comprises: an input, arranged to receive the clock signal; a clock divider, configured to divide the received clock signal and provide a divided clock signal; a calibration buffer, configured to adjust the divided clock signal, the input clock signal of the time-to-digital converter being the adjusted divided clock signal; and NMA processing logic, configured to receive the measurement output from the time-to-digital converter and generate the parameter indicative of an effective cycle time of the clock signal.

[0011] In embodiments, the AFS circuit comprises: a supply pin voltage input, arranged to receive a supply pin voltage for the IC; a filter, configured to process the received supply pin voltage and generate a PLL filter input for input to a phase-locked loop (PLL) of a clock generator; and AFS processing logic, configured to receive the output of the NMA and, in response to the received output of the NMA, control the PLL output. In embodiments, the PLL filter input is provided as an input to the PLL for summation with an output of a low pass filter of the PLL and/or as a component of an input to a signal generator of the PLL.

[0012] In embodiments, the AFS circuit comprises: AFS processing logic, comprising clock selection logic configured to select from one of a plurality of clock generator circuits, each clock generator circuit being configured to generate a clock signal of a respective, different frequency, the clock signal generated by the selected clock generator circuit providing the clock signal in the semiconductor IC.

[0013] In embodiments, the AFS processing logic is configured to control activation of the PLL filter input or clock selection logic and/or adjust the PLL filter input or clock selection logic, in response to the received output of the NMA.

[0014] According to further embodiments, there may be provided a semiconductor integrated circuit (IC) comprising a clock generation circuit and a controller for generation of a clock signal as herein disclosed.

[0015] In accordance with other embodiments, there is provided a method for generating a clock signal in a semiconductor integrated circuit (IC), the method comprising: measuring the clock signal to provide a parameter indicative of an effective cycle time of the clock signal; and selectively adjusting a frequency of the clock signal based on the parameter indicative of the effective cycle time of the clock signal, using an Adaptive Frequency Scaling (AFS) circuit.

[0016] In embodiments, the method further comprises activating adjusting or switching a frequency of the clock signal if the parameter indicative of the effective cycle time of the clock signal descends below a first threshold. In embodiments, the method further comprises deactivating adjusting or switching a frequency of the clock signal if the parameter indicative of the effective cycle time of the clock signal rises above a second threshold, the second threshold being higher than the first threshold.

[0017] In embodiments, the method further comprises: when the AFS circuit is activated, reducing the frequency of the clock signal in response to the parameter indicative of the effective cycle time of the clock signal indicating a reduction in the effective cycle time of the clock signal.

[0018] In embodiments, the step of measuring the clock signal to provide a parameter indicative of an effective cycle time of the clock signal is performed by a Noise Modulation Agent (NMA), the parameter indicative of the effective cycle time of the clock signal being an output of the NMA.

[0019] In embodiments, the NMA comprises a time-to-digital converter, arranged to output a measurement of a cycle time of an input clock signal, the parameter indicative of an effective cycle time of the clock signal being based on the measurement output of the time-to-digital converter. In embodiments, the method further comprises: receiving the clock signal at the NMA; dividing the received clock signal to provide a divided clock signal; adjusting the divided clock signal using a calibration buffer; measuring a cycle time of the adjusted divided clock signal at the time-to-digital converter; and generating the parameter indicative of an effective cycle time of the clock signal using the measurement output from the time-to-digital converter.

[0020] In embodiments, the method further comprises: receiving a supply pin voltage for the IC; processing the received supply pin voltage at a filter and generating a PLL filter input for input to a phase-locked loop (PLL) of a clock generator; and receiving the parameter indicative of the effective cycle time of the clock signal and, in response to the received parameter indicative of the effective cycle time of the clock signal, controlling the PLL output.

[0021] In embodiments, the method further comprises: selecting from one of a plurality of clock generator circuits, each clock generator circuit being configured to generate a clock signal of a respective, different frequency, the clock signal generated by the selected clock generator circuit providing the clock signal in the semiconductor IC. [0022] In embodiments, the method further comprises controlling activation of the PLL filter input or the step of selecting and/or adjusting the PLL filter input or the step of selecting, in response to the received parameter indicative of the effective cycle time of the clock signal.

[0023] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the figures and by study of the following detailed description. The skilled person will appreciate that combinations and sub-combinations of specific features disclosed herein may also be provided, even if not explicitly described.

BRIEF DESCRIPTION OF THE FIGURES

[0024] Exemplary embodiments are illustrated in referenced figures. Dimensions of components and features shown in the figures are generally chosen for convenience and clarity of presentation and are not necessarily shown to scale. The figures are listed below.

[0025] Figure 1 shows example clock and data waveforms from a semiconductor IC, showing margins due to noise.

[0026] Figure 2 schematically illustrates an example Noise Modulation Agent (NMA). [0027] Figure 3 shows example simulated noise on a power supply pin voltage of a semiconductor IC.

[0028] Figure 4A plots a first example of a readout from a time-to-digital converter of a NMA according to Figure 2, when measuring a clock signal with noise.

[0029] Figure 4B shows the plot of Figure 4A overlaid on the simulated noise of Figure 3, to compare the two.

[0030] Figure 5 schematically depicts a typical core clock generation and distribution circuit for a semiconductor IC.

[0031] Figure 6 schematically depicts an example clock generation and distribution circuit for a semiconductor IC with a first implementation of Adaptive Frequency Scaling (AFS).

[0032] Figure 7 schematically depicts an example clock generation and distribution circuit for a semiconductor IC with a second implementation of AFS.

[0033] Figure 8 schematically depicts a clock generation and distribution circuit for a semiconductor IC with AFS controlled by an output of a NMA.

[0034] Figure 9 shows the readout of Figures 4B and 5, illustrating an example control of AFS using the readout from a time-to-digital converter of a NMA.

[0035] Figure 10 plots a second example of a readout from a time-to-digital converter of a NMA, together with a corresponding power supply pin voltage of a semiconductor IC, further illustrating an example control of AFS.

DETAILED DESCRIPTION

[0036] Disclosed herein are devices, systems, and methods to control generation of a clock signal in a semiconductor integrated circuit (IC). Noise may cause a droop in the power supply pin voltage (VDD) of the semiconductor IC. VDD droop may then lead to clock frequency reduction. Adaptive Frequency Scaling (AFS) is able to control the clock frequency and, in response to detection of a VDD droop, maintain the clock frequency at the desired level. [0037] A Noise Modulation Agent (NMA) can be used to measure an effective cycle time of the clock signal. It has been found by the inventors that an output of the NMA can indicate VDD droop. Using this output to control VDD operation can therefore advantageously provide improved AFS operation and better clock frequency control. [0038] Reference is made to Figure 1, which shows an example clock waveform 10, having a cycle period (T _cyc ) and an example data waveform 20 from a semiconductor IC, showing margins due to noise. Changes in the data waveform 20 typically occur at clock signal edges, as illustrated. A logic path within the semiconductor IC, for example resulting in data waveform 20, is designed to meet a certain clock cycle time. For example, if a certain logic path should be run at a clock signal of frequency 1 GHz, the propagation delay (P delay) of the logic path (assuming it is a critical path) should be no more than 1 nanosecond (less any flip-flop setup time, Setup time) to avoid a timing error. The time duration between a change in the data waveform 20 and the next rising edge of the clock waveform 10 may be termed a “margin.” This provides a quantitative expression of how well the designed propagation delay is being met.

[0039] The above discussion represents an ideal case, that is, where there is substantially no noise in the system. In a real system, the propagation delay (P delay) is affected by the noise. As a result, the margin to failure (M) is also affected: M = T _cyc — P_delay — Setupjime. The margin (M) is typically affected by one or both of two noise sources: power supply noise, represented by voltage noise 30 and causing noise in the data waveform 20; and/or clock jitter, represented by timing noise 40, causing noise in the clock signal edges and thereby affecting the clock frequency.

[0040] A nominal margin 50 may therefore be considered based on the duration between an average time for a change in the data waveform 20 and an average time for a next rising edge of the clock waveform 10. A modulated margin 60 may be considered based on the duration between a latest time for a change in the data waveform 20 (due to voltage noise 30) and an earliest time for a next rising edge of the clock waveform 10 (due to timing noise 40 - a Gaussian timing noise illustrated on both sides of the rising clock edge, but only the maximum of its negative amplitude should be taken into account). The effective cycle time for the clock signal may therefore be considered the nominal or average cycle time subtracted by the modulated margin 60. For example, a logic path may be designed to meet a clock cycle time of 1 ns at a VDD of nominal amplitude (VDD-nom). If the voltage noise level is -20 mV, the propagation delay of the path will increase, so in order to meet a setup time of a sampling flip-flop at the end of the logic path, the cycle time should be effectively increased. In other words, the effective cycle time of a logic block may be considered equivalent to the minimum operational cycle time (or conversely, the time corresponding with the maximum operational frequency) of a logic system, considering voltage noise and clock jitter. [0041] The effective cycle time can be measured by a NMA. With reference to Figure 2, there is schematically illustrated an example NMA 110. The NMA 110 comprises: a clock divider 111; a trimmable calibration buffer 113; a time-to-digital converter (TDC) 116; a controller 118; and registers for determining minimum and/or maximum values 119. A clock source 100 provides a clock signal 105 (rl clk) to the clock divider 111, which provides a divided clock signal 112. Typically, the clock signal 105 is divided by 2, only when clock source is between 2 GHz and 4 GHz.

[0042] The divided clock signal 112 is provided as an input to the trimmable calibration buffer 113, which is controlled by the controller 118. The trimmable calibration buffer

113 adjusts the divided clock signal 112 and provides an adjusted divided clock signal

114 to the TDC 116. The TDC also receives the IC supply pin voltage (VDD) 115 and provides a digital time output 117 to the controller 118 and to the registers 119. The registers also receive the divided clock signal 112. The digital time output 117 is encoded in an 8-bit register in registers 119 and is ready two clock source cycles after the TDC measurement. The registers 119 provide a serial data output 120 based on the digital time output 117 and the divided clock signal 112. Calibration is carried out every time the NMA starts a measurement (monitoring) period.

[0043] As discussed above, noise on the power supply voltage may cause VDD droop. This can be detected by the NMA. For example, consider a clock signal Vclk(t) that has an angular frequency coo and an overlaid noise signal Vn(t) = V _m cos(co _m t). The change in the clock period is given by the following expression:

[0044] The output of the TDC 116 represents the effective clock cycle time. The TDC 116 uses a tapped delay line with flip-flops arranged at each tap. The effective clock cycle time is determined by a combination of the variation in the clock cycle-time input to the TDC 116 and the impact of the VDD noise on the delay -line of the TDC 116. Therefore, the VDD droop effect due to the noise is indicated by the TDC output. This is discussed further below using an example. [0045] With reference to Figure 3, there is shown example simulated noise on a power supply pin voltage of a semiconductor IC. This shows the VDD droop effect for a clock signal of frequency 1600 MHz.

[0046] With reference to Figure 4A, there is plotted a first example of a readout from a TDC of a NMA according to Figure 2 when measuring the simulated clock signal with noise of Figure 3. Figure 4B, in turn, illustrates the simulated noise of Figure 2 overlaid on the TDC readouts of Figure 4B, for comparison. As can be seen, the two correlate: the TDC output drops significantly at the same time as the VDD output, and vice versa. It has therefore been recognized that it would be useful to use the TDC output in controlling the clock frequency. An implementation to effect such control is now discussed.

[0047] In general terms, there may be considered a controller for generation of a clock signal in a semiconductor integrated circuit (IC), the controller comprising: a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal; and an Adaptive Frequency Scaling (AFS) circuit, configured selectively to adjust a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC. In a corresponding aspect, there may be considered a method for generating a clock signal in a semiconductor IC, the method comprising: measuring the clock (in particular, using a NMA) to provide a parameter indicative of an effective cycle time of the clock signal; and selectively adjusting a frequency of the clock signal, based on the parameter indicative of the effective cycle time of the clock signal indicating a change in a power supply voltage of the semiconductor IC, using an AFS circuit. A semiconductor IC comprising a clock generation circuit and a controller for generation of a clock signal according to the present disclosure may further be considered.

[0048] Various features may be applicable to any of these aspects. For example, the NMA may comprise a time-to-digital converter (TDC). The TDC may be arranged to output a measurement of a cycle time of an input clock signal, the parameter indicative of an effective cycle time of the clock signal being based on the measurement output of the time-to-digital converter. The TDC may comprise a tapped delay line. The NMA may further comprise: an input, receiving the clock signal; a clock divider, dividing the received clock signal to provide a divided clock signal; a calibration buffer, adjusting the divided clock signal, the input clock signal of the TDC being the adjusted divided clock signal. Advantageously, the NMA also comprises NMA processing logic, receiving the measurement output from the TDC and generating the parameter indicative of an effective cycle time of the clock signal. The clock divider and/or the calibration buffer may be omitted, in which case, the input clock signal of the TDC may be the divided clock signal or an adjusted clock signal (an output of the calibration buffer). [0049] Specific details of exemplary implementations will now be discussed and further features according to these general terms will be referenced again subsequently.

[0050] With reference to Figure 5, there is schematically depicted a typical core clock generation and distribution circuit for a semiconductor IC. This comprises: a Phase- Locked Loop (PLL) clock generator 210; and a clock network 230. The PLL clock generator 210 comprises: a phase detector 211; a low pass filter 212; a voltage controller oscillator (VCO) 213; and a frequency divider 214. The PLL clock generator 210 also receives an Analog Supply Voltage (VDDA) 205. The operation of the PLL clock generator 210 is standard and well understood in the technical field. The phase detector 211 receives a reference clock signal 200 and the output of the frequency divider 214 and generates an error signal that is proportional to the phase difference of these two inputs. That error signal is passed through the low pass filter 212 and the output controls the VCO 213. The output of the VCO 213, which is the PLL clock output 220, is fed back via the frequency divider 214 to the phase detector 211. The PLL clock output 220 is also provided to the clock network 230, which also receives the core supply voltage (VDD Core) 240. The output of the clock network 230 provides a core clock 250. [0051] With reference to Figure 6, there is schematically depicted an example clock generation and distribution circuit for a semiconductor IC with a first implementation of Adaptive Frequency Scaling (AFS). As discussed above, AFS is used to control the clock frequency and counteract the effects of VDD droop. Where the same features as described in relation to another drawing are shown, identical reference numerals have been used.

[0052] The PLL clock generator 310 comprises the same features as the PLL clock generator 210 discussed with reference to Figure 5. The PLL clock generator 310 additionally includes: a tunable AFS filter 320; and a signal adder 345. The tunable AFS filter 320 receives the VDD core 325 and, based on a AFS configuration input 330, produces an AFS output signal 340. This is added to the output of the low pass filter 212 by the signal adder 345 and the summed output is provided as the input to the VCO 213. When VDD droop is detected, the AFS system is activated. In particular, the AFS system is configured to reduce the clock frequency at least until the transient VDD droop has subsided. The tunable AFS filter 320 may dynamically effect scaling of the core clock 250 to different levels, as required in view of the AFS configuration input 330. The tunable AFS filter 320 may be configured, accordingly, to produce such AFS output signal 340 that effects differing levels of core clock 250 frequency correspondingly to the evolving VDD droop.

[0053] Optionally, the tunable AFS filter 320 may be configured, by the AFS configuration input 330, to change its attenuation respective of the incident VDD level. This may be done in a manner which reflects an expected change in sensitivity to VDD noise amplitudes at different VDD levels. For example, the AFS configuration input 330 may configure the tunable AFS filter 320 to perform attenuation to a first, predefined level upon a certain first VDD value, and to attenuate to a second, predefined level upon a certain second VDD value.

[0054] AFS methods other than that shown in Figure 6 are possible. With reference to Figure 7, there is schematically depicted an example clock generation and distribution circuit for a semiconductor IC with a second implementation of AFS. This alternative AFS method uses two (or more) clock generators, specifically first clock generator 311 and second clock generator 312, instead of a single clock generator 310 (based on a tunable AFS filter 320) of Figure 6. Each of the first clock generator 311 and second clock generator 312 is structurally the same and as shown in Figure 5, for instance. Where the same features as described in relation to Figure 5 are shown, identical reference numerals have been used.

[0055] Each of the first clock generator 311 and second clock generator 312 is configured to generate a clock signal of a different clock frequency. Specifically: the first clock generator 311 is configured to generate a first PLL clock output 221 at a first clock frequency, f clk l; and the second clock generator 312 is configured to generate a second PLL clock output 222 at a second clock frequency, f_clk_2, wherein f_clk_l > f_clk_2 (for example, f clk l = 1.1 x f_clk_2). An AFS control circuit or clock switching block 350 rapidly switches between the two clock generators to provide a clock output 225 dependent on the VDD droop detected. For example, AFS configuration input 330 may be a control signal, that instructs the clock switching block 350 whether to output f_clk_l or f_clk_2 as the clock output 225. The AFS configuration input 330, as previously discussed, may be affected by whether VDD droop has been detected or not. For example, the control signal which the AFS configuration input 330 provides may be 1 (high) when no AFS is required, and 0 (low) when AFS has to be activated in order to counteract the VDD droop. The opposite is also possible, of course. The average duty cycle of the control signal then reflects the average system performance.

[0056] Embodiments according to the disclosure may use any AFS technique.

[0057] As an alternative to the configuration of Figure 7, a single clock generator may be used instead of the multiple clock generators shown in this figure, and a clock divider may be added to the configuration so as to divide the clock signal of that single clock generator into multiple (two or more) clock signals of different frequencies. The AFS control circuit or clock switching block then rapidly switches between these multiple clock signals to provide a clock output dependent on the VDD droop detected.

[0058] With reference to Figure 8, there is schematically depicted a clock generation and distribution circuit for a semiconductor IC with AFS controlled by an output of a NMA. Most features of this figure are the same as shown in Figure 6 (with the same reference numerals are used to show the same features), except for the following: Additionally shown in Figure 8 is NMA 400, which receives the core clock 250 and the VDD Core voltage 325 and uses these to generate an NMA output 410 (as discussed above with reference to Figure 2). Alternatively, if it is desired to avoid a feedback loop configuration, NMA 400 may receive the signal of a different clock 252 instead of core clock 250. This may be useful, for example, to achieve DVFS (Dynamic Volage and Frequency Scaling) functionality, as the dynamically-adjusted frequency of the core clock 250 will not affect the operation of NMA 400.

[0059] The NMA output 410, optionally subject to some further processing, is then used to derive the AFS configuration signal 330, to provide feedback to the AFS thereby. This may include operating the example clock generation and distribution circuit of Figure 6 in a feedback loop mode, in which NMA 400 readouts continue to be taken while AFS is active, and the tunable AFS filter 320 is tuned, in real time, respective of these readouts: If one or more consecutive readouts (e.g., 1-5, 1-10, or 1-20 readouts) indicate that the effect of the AFS is insufficient (an undercompensation scenario), the tunable AFS filter 320 may be immediately controlled by the AFS configuration input 330 to effect further reduction of frequency. Conversely, if one or more consecutive readouts (e.g., 1-5, 1-10, or 1-20 readouts) indicate that the effect of the AFS is excessive (overcompensation), the tunable AFS filter 320 may be immediately controlled by the AFS configuration input 330 to effect an increase of frequency (or even complete deactivation of AFS). The same level in the tunable AFS filter 320 may be kept if the compensation is deemed proper.

[0060] In case a DVFS functionality is desired, and NMA is configured to receive clock signal 252 instead of a signal from core clock 250, then an input (not shown) to the clock divider /N may dictate the frequency scaling, so as to affect the frequency of PLL clock 220 and subsequently core clock 250.

[0061] Similar to the embodiment of Figure 8, also the embodiment of Figure 7 may be operated in a feedback loop mode. In this mode (not shown), NMA (TDC) readouts continue to be taken when AFS is active, and the AFS configuration input instructs the clock switching block to maintain current frequency or switch to the other frequency, respective of the NMA readouts.

[0062] Returning to the general terms discussed above, further details can now be described. For example in some embodiments, the AFS circuit may comprise AFS processing logic configured to receive the output of the NMA (parameter indicative of the effective cycle time of the clock). and control AFS operation in response to the received output of the NMA.

[0063] In certain embodiments, the AFS circuit may further comprise: a supply pin voltage input, arranged to receive a supply pin voltage for the IC; and a filter, configured to process the received supply pin voltage and generate a PLL filter input for input to a phase-locked loop (PLL) of a clock generator. Then, the AFS processing logic may be configured to control the PLL output in response to the received output of the NMA. The PLL filter input may be provided as an input to the PLL for summation with an output of a low pass filter of the PLL and/or as a component of an input to a signal generator of the PLL.

[0064] In some embodiments, the AFS processing logic comprises clock selection logic. The clock selection logic selects from one of a plurality of clock generator circuits, each clock generator circuit being configured to generate a clock signal of a respective, different frequency. The clock signal generated by the selected clock generator circuit advantageously provides the clock signal in the semiconductor IC.

[0065] According to certain embodiments, activation of the PLL filter input or clock selection logic may be controlled (by the AFS processing logic). Additionally or alternatively, the PLL filter input or clock selection logic may be adjusted (by the AFS processing logic), in response to the received output of the NMA (parameter indicative of the effective cycle time of the clock). [0066] With reference to Figure 9, there is shown, with a continuous curve, the NMA (TDC) readout of Figures 4B and 5. There is also shown, with a dotted curve, a possible NMA (TDC) readout with AFS active, optionally in accordance with the embodiment of Figure 7 which makes use of a tunable AFS filter. As shown, there is a substantial VDD droop occurring between clock cycles 0 and 1, detected by the NMA. AFS is then activated, and its effect is seen after brief response time of a few clock cycles, at clock cycle 4. Next, it is shown that AFS is able to adjust the core clock frequency such that the NMA (TDC) readouts are kept at a substantially higher level than what their level had been absent AFS: on average, between clock cycles 4 and 48, the result of activating the AFS is an approximate 15-20% increase in NMA readouts, which represent the average frequency compensation (average increase in the clock cycle time) that is needed to compensate the dynamic voltage droop.

[0067] With reference to Figure 10, there is plotted a second example of a readout from a time-to-digital converter of a NMA, together with a corresponding power supply pin voltage 600 of a semiconductor IC, further illustrating an example control of AFS. This second example uses an AFS technique according to the alternative approach described above using two clock generators, with reference to Figure 8. A first (lower) threshold 610 in respect of the NMA readout is used to determine that VDD droop is occurring and that AFS should therefore be activated. The clock frequency is therefore switched from higher frequency f_clk_l to lower frequency f_clk_2. A second (upper) threshold 630 is used to determine that VDD droop is no longer taking place and the AFS should therefore be deactivated. As a result, the clock frequency is switched from lower frequency f_clk_2 back to higher frequency f clk l .

[0068] The first threshold 610 and the second threshold 630 are optionally determined in relation to a reference level 620. In this example, the reference level 620 is set to correspond with a NMA (TDC) readout of 10. The first threshold 610 is set to be at an activation level below the reference level 620. In this example, the activation level is set as 2, so the first threshold is set as 8. The second threshold 630 is set to be at a deactivation level above the reference level 620. In this example, the deactivation level is set as 2, so the second threshold is set as 12. By differentiating the first threshold 610 and the second threshold 630, a hysteresis effect is possible, which allows better operation of the AFS system.

[0069] Again referencing the general terms discussed above, further features may be considered. For example, the frequency of the clock signal may be adjusted (by activating the AFS circuit) if the output of the NMA (parameter indicative of the effective cycle time of the clock) descends below a first threshold. In some embodiments, a frequency of the clock signal may be adjusted back to its original value (by deactivating the AFS circuit) if the output of the NMA (parameter indicative of the effective cycle time of the clock) rises above a second threshold. The second threshold is advantageously higher than the first threshold.

[0070] In certain embodiments, when the AFS circuit is activated, the frequency of the clock signal may be reduced (by the AFS circuit) in response to the output of the NMA indicating a reduction in the effective cycle time of the clock signal.

[0071] In addition to the exemplary AFS activation points and thresholds discussed above with reference to Figures 9 and 10, any threshold-based or other rule-based mechanism to determine when to activate and deactivate an AFS circuit (or how to tune a tunable AFS circuit) based on the NMA (TDC) readout is intended herein.

[0072] The system may be operated in two modes. In AFS characterization mode, the NMA readout is used to tune the system response against VDD core level. Different tuning for different VDD levels may be set to avoid overcompensation and/or under compensation. At a tester (off chip), the NMA readout can be used to tune the system response against a logic test (for VDD noise). At the system, the NMA readout can be used to tune the system response for each application. In a mission mode, the NMA readout can be used to protect the PLL from out-of-range voltage noise. When implementing AFS according to the first implementation (as shown in Figure 6), there may be a concern that the AFS output signal 340, based on filtering the VDD noise amplitude and injected to the VCO 213 may be higher than a certain maximum limit. This may take the PLL out of lock. In this mode, the NMA readout may be used to mitigate such problems.

[0073] The NMA devices may be placed in timing-sensitive units. This may include placing them in the same blocks as Margin Agents (such as described in International Patent Application Publication No. WO2019/202595 Al, commonly assigned with the present application, and incorporated herein by reference in its entirety). The NMA device may be straightforward to integrate with the IC and operate in-situ.

[0074] Throughout this disclosure, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0075] Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging/ranges between” a first indicate number and a second indicate number and “ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

[0076] In the description and claims of the disclosure, each of the words “comprise” “include” and “have”, and forms thereof, are not necessarily limited to members in a list with which the words may be associated. In addition, where there are inconsistencies between this application and any document incorporated by reference, it is hereby intended that the present application controls.

[0077] To clarify the references in this disclosure, it is noted that the use of nouns as common nouns, proper nouns, named nouns, and the/or like is not intended to imply that embodiments of the invention are limited to a single embodiment, and many configurations of the disclosed components can be used to describe some embodiments of the invention, while other configurations may be derived from these embodiments in different configurations.

[0078] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It should, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application- and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0079] Based upon the teachings of this disclosure, it is expected that one of ordinary skill in the art will be readily able to practice the present invention. The descriptions of the various embodiments provided herein are believed to provide ample insight and details of the present invention to enable one of ordinary skill to practice the invention. Moreover, the various features and embodiments of the invention described above are specifically contemplated to be used alone as well as in various combinations.

[0080] Conventional and/or contemporary circuit design and layout tools may be used to implement the invention. The specific embodiments described herein, and in particular the various circuit arrangements, measurements and data flows, are illustrative of exemplary embodiments, and should not be viewed as limiting the invention to such specific implementation choices. Accordingly, plural instances may be provided for components described herein as a single instance. The determination of margin and/or other parameters may be made in different parts of the configuration, for example. The design of PLL and/or AFS shown and discussed in the disclosure may be varied and approaches in accordance with the disclosure may be applied to other types of PLL and/or AFS. Additionally or alternatively, the approach for integrating the NMA readout with AFS may be varied from that described herein.

[0081] While circuits and physical structures are generally presumed, it is well recognized that in modem semiconductor design and fabrication, physical structures and circuits may be embodied in computer readable descriptive form suitable for use in subsequent design, test or fabrication stages as well as in resultant fabricated semiconductor integrated circuits. Accordingly, claims directed to traditional circuits or structures may, consistent with particular language thereof, read upon computer readable encodings (which may be termed programs) and representations of same, whether embodied in media or combined with suitable reader facilities to allow fabrication, test, or design refinement of the corresponding circuits and/or structures. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. The invention is contemplated to include circuits, systems of circuits, related methods, and computer-readable (medium) encodings of such circuits, systems, and methods, all as described herein, and as defined in the appended claims. As used herein, a computer readable medium includes at least disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory cards, ROM), or electronic medium and a network, wireline, wireless or other communications medium.

[0082] The foregoing detailed description has described only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended by way of illustration, and not by way of limitations. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention. It is only the following claims, including all equivalents, which are intended to define the scope of this invention. Moreover, the techniques described herein may also be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may fall within the scope of the invention as defined in the claims that follow.

[0083] Embodiments of the present invention may be used to fabricate, produce, and/or assemble integrated circuits and/or products based on integrated circuits.

[0084] Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

[0085] The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0086] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.