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Patent Searching and Data


Title:
ADAPTIVE GATE-BIAS REGULATOR FOR OUTPUT BUFFER WITH POWER-SUPPLY VOLTAGE ABOVE CORE POWER-SUPPLY VOLTAGE
Document Type and Number:
WIPO Patent Application WO/2024/021170
Kind Code:
A1
Abstract:
A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal ofa buffer that drives the gate ofthe cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, avoltage boost is provided to the gates ofthe cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.

Inventors:
CHAN CHIT SANG (CN)
YAM CHUN KIT (CN)
Application Number:
PCT/CN2022/111857
Publication Date:
February 01, 2024
Filing Date:
August 11, 2022
Export Citation:
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Assignee:
HONG KONG APPLIED SCIENCE & TECH RESEARCH INST CO LTD (CN)
International Classes:
H03K19/0185
Foreign References:
US20070052445A12007-03-08
US20020186058A12002-12-12
US20070279096A12007-12-06
US20100264974A12010-10-21
US20110025380A12011-02-03
Attorney, Agent or Firm:
CHINA PATENT AGENT (H.K.) LTD. (CN)
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