ADAPTIVE SIGNAL EQUALIZER

WITH SEGMENTED COARSE AND FINE CONTROLS

RELATED APPLICATION DATA

This application is a non-provisional based on and claiming priority from U.S.

Provisional Application No. 61/365,531, filed July 19, 2010.

BACKGROUND

1. Field of the Invention

The present invention relates to interface circuits for receiving high data rate signals from long lengths of cable, and in particular, interface circuits for receiving high data rate, baseband, binary encoded data signals from long lengths of cable.

2. Description of the Related Art

In a typical high speed digital wire-line communication system, the channel introduces frequency dependent loss. These losses cause inter-symbol interference (ISI) when the channel is conveying a random data pattern. An equalizer removes the ISI by implementing the inverse channel response that compensates for the signal distortion caused by the channel. An adaptive equalizer automatically compensates for the loss of the channel.

Recovering data which has been transmitted over a long length of cable at high rates requires that such data be equalized in order to compensate for the loss and phase dispersion of the cable. Further, in those applications where the cable length may vary, such equalization must be based upon a complementary transfer function which is capable of adapting accordingly since the transfer function of the cable varies with the length of the cable. This equalizing is generally done using three functions: a filter function; a dc restoration and slicing function; and an adaptation control, or servo, function. The filter function is performed using a complementary (with respect to the complex cable loss characteristic) filter which synthesizes the inverse of the transfer function of the cable. Since the bit error rate (BER) is directly related to jitter, an important performance metric for an equalizer is jitter within the output waveform. The extent to which the equalizer is able to match the inverse of the complex cable loss characteristic determines the extent to which inter-symbol interference induced jitter is eliminated.

Conventional equalizers use gm/C types of continuous time filters or finite impulse response (FIR) filters. However, these types of filter structures tend to be complex and have difficulty maintaining the required balance among the desired operating characteristics, such as output jitter, compensation for process and temperature variations, and optimization of the signal-to-noise ratio (SNR).

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a functional block diagram of an adaptive signal equalizer in accordance with a preferred embodiment.

Figure 2 is a functional block diagram of an exemplary embodiment of the high rate filter of Figure 1.

Figure 3 is a functional block diagram of an exemplary embodiment of the low rate filter of Figure 1.

Figure 4 is a functional block diagram of an exemplary embodiment of the DC restoration and slicer stages of Figure 1.

Figure 5 is a functional block diagram of an exemplary embodiment of the adaptation stages of Figure 1.

Figure 6 is a functional block diagram of an alternative embodiment of the integration and summing stages of Figure 5.

Figure 7 is a functional block diagram of an exemplary embodiment of a signal conversion stage for use as part of the adaptation stages of Figure 1.

Figure 8 is a functional block diagram of an exemplary embodiment of the control stage of Figure 1. Figure 9 is a state diagram of an exemplary embodiment of an algorithm used by the finite state machine of Figure 8.

Figure 10 is a schematic diagram of an exemplary embodiment of the equalization circuits of Figures 2 and 3.

Figure 11 is a partial schematic diagram of an exemplary embodiment of an AC portion of the equalization circuit stages of Figure 10.

Figure 12 is a diagram depicting an exemplary embodiment of a step- wise linear control for the fine tuning of equalization.

Figure 13 is a timing diagram of an exemplary embodiment of timing for coarse and fine boost up equalization adjustments.

Figure 14 is a timing diagram of an exemplary embodiment of timing for coarse and fine boost down equalization adjustments.

Figure 15 is a functional block diagram of an exemplary embodiment of the rate detection stage of Figure 1.

DETAILED DESCRIPTION

The following detailed description is of example embodiments with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of all possible embodiments. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice them, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention.

Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms "circuit" and "circuitry" may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term "signal" may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. Moreover, to the extent that the figures illustrate diagrams of the functional blocks of various embodiments, the functional blocks are not necessarily indicative of the division between hardware circuitry. Thus, for example, one or more of the functional blocks (e.g., processors, memories, etc.) may be implemented in a single piece of hardware (e.g., a general purpose signal processor, random access memory, hard disk drive, etc.). Similarly, any programs described may be standalone programs, may be incorporated as subroutines in an operating system, may be functions in an installed software package, etc.

An adaptive signal equalizer in accordance with one or more preferred embodiments includes one or more of a number of features. Adaptive equalization can be provided with separate equalization boost and amplitude control loops. Adaptive equalization can also be provided with different equalization characteristics depending upon whether a higher or lower data rate is received. Adaptive equalization can be further provided using an initial binary search to reduce the number of necessary data points to be analyzed before reaching the desired equalization, and may include an initial equalization setting (e.g., based on control data stored in a lookup table). The equalization circuit architecture includes coarse control, and may also include fine control, along with means for controlling the transition between coarse and fine adjustments in the equalization.

Adaptation of the equalization is based on interlaced successive approximation of digital boost and amplitude codes. Energy detection points are separated for high data rate and low data rate equalization paths. Different filter bandwidths are used for adaption based on high and low data rates. Boost-dependant amplitude calibration provides a higher calibration range. Power consumption and thermal noise are reduced in the equalization data paths compared to conventional analog adaptation techniques. Further power consumption and thermal noise reductions are achieved by avoiding the use of an automatic gain control (AGC) stage for DC amplitude calibration. Interactions between the amplitude and equalization boost control loops and deadlock are reduced. Linear equalization is segmented to allow for optimal equalization for multiple channels. Both coarse and fine equalization boosts are provided, with appropriate timing when transitioning between coarse and fine adjustments and when increasing or decreasing the digital boost codes. Data rate detection is provided to differentiate between high (e.g., 1.485 Gbps) and low (e.g., 270 Mbps) data rates, with such rate detection used to control the adaptation algorithm. Separate filter bandwidths for high and low data rate paths minimize crosstalk and improve noise performance independently.

Referring to Figure 1, an adaptive signal equalizer 100 in accordance with one embodiment includes multiple stages interconnecting and interacting substantially as shown: a high (data) rate filter stage 102, a high rate DC restoration and slicing stage 104, a high rate adaptation stage 106, a low (data) rate filter stage, 112, a low rate DC restoration and slicing stage 114, a low rate adaptation stage 116, a signal multiplexor 118, a rate detection stage 130 and a control stage 120. As discussed in more detail below, high data rate signals are processed by the high rate filter 102, high rate DC restoration and sheer 104 and high rate adaptation 107 stages, while low data rate signals are processed by the low rate filter 112, low rate DC restoration and sheer 114 and low rate adaptation 116 stages (e.g., with the high rate filter stage 102 set for less equalization or unity signal gain with no equalization). In accordance with a rate detection signal 131 (which is indicative of whether the incoming signal 101 has a high or low data rate), the multiplexor 118 provides the equalized high 105 or low 115 data signal as the equalized output signal 119.

The high rate filter stage 102 provides controllable amounts of equalization in accordance with high rate coarse 125 and fine 127 control signals. The resulting equalized signal 103 is DC- restored and sliced by the DC restoration and sheer stage 104 in accordance with an amplitude control signal 121 (discussed in more detail below).

This equalized signal 103 is further equalized by the low rate filter 112 in accordance with low rate coarse 129 and fine 127 equalization control signals (discussed in more detail below). The resulting equalized signal 113 is DC-restored by the DC restoration and sheer stage 114 in accordance with the amplitude control signal 121.

The first equalized signal 103 is also used by the rate detection stage 130 to determine whether the incoming signal 101, as represented by the first equalized signal 103, has a high data rate or a low data rate. Its output signal 131 is indicative of the data rate (e.g., high or low).

One of the DC-restored and sliced signals 105, 115 is selected by the multiplexor 118, in accordance with the rate detection signal 131, as the equalized output signal 119. For example, if the rate detection signal 131 is indicative of an input signal 101 having a high data rate, the high rate equalized signal 105 is selected. Conversely, if the rate detection signal 131 is indicative of the incoming signal 101 having a low data rate, the low rate equalized signal 115 is selected.

The high rate adaptation stage 106 processes the equalized input signal 103 and DC- restored and sliced signal 105 of the first DC-restoration and slicer stage 104 to provide a feedback signal 107 to the control stage 120 (discussed in more detail below). Similarly, the low rate adaptation stage 116 processes the low rate equalized signal 113 and DC-restored and sliced signal 115 of the second DC restoration and slicer stage 114 to provide another feedback signal 117 to the control stage 120 (discussed in more detail below).

As discussed in more detail below, the control stage 120 receives and processes the adaptation feedback signals 107, 117 and rate detection signal 131 to provide the amplitude control signal 121, a reset signal 123 and equalizer boost control signals 125, 127, 129.

Referring to Figure 2, an exemplary embodiment of the high rate filter stage 102 includes four equalizer circuits 202a, 202b, 202c, 202d and a digital-analog converter (DAC) 202e, interconnected substantially as shown. The incoming signal 101 is successively equalized by each equalizer circuit 202a, 202b, 202c, 202d to produce the first equalized signal 103. Each equalizer circuit 202a, 202b, 202c, 202d is controlled in accordance with a respective subset 125a, 125b, 125c, 125d of the high rate coarse equalization control signal 125. In this exemplary embodiment, the 24-bit control signal 125 is split into four respective 6-bit control signals. The fine equalization control signal 127 is converted by the DAC 202e to an analog control voltage Vfme 203 e for fine tuning the equalization performed by each equalization circuit 202a, 202b, 202c, 202d (discussed in more detail below).

In accordance with a preferred embodiment, these four equalizer circuits 202a, 202b, 202c, 202d provide a total of 60 dB of maximum boost (e.g., 15 dB per circuit), using six coarse steps corresponding to 2.5 dB boost per step, and 32 fine steps, thereby providing a resolution of 0.08 dB. The coarse boost control signal 125 use a thermometer code, so the fine boost signal 127 can be shared across all equalizer circuits 202a, 202b, 202c, 202d, i.e., as the converted analog control voltage 203e.

Referring to Figure 3, an exemplary embodiment of the low rate filter stage 112 includes an equalization circuit 212a and a DAC 212b, interconnected substantially as shown. The first equalized signal 103 is further equalized by the equalization circuit 212a to produce the second equalized signal 113. Coarse adjustment of the equalization is in accordance with the low rate coarse control signal 129, while fine adjustment of the equalization is done in accordance with an analog control voltage 213b provided by the DAC 212b based on the fine control signal 127.

This equalizer circuit 212a includes seven internal stages (discussed in more detail below), resulting in seven coarse steps, each of which is further divided into 32 fine steps. As with the high rate filter stage 102, the coarse boost follows a thermometer code, so the fine boost lines can all be driven by the same analog control signal 213b.

Accordingly, in accordance with a preferred embodiment, the four stages of equalization within the high rate filter 102 provides 768 fine steps (6 * 32 * 4 = 768), and the low rate filter stage 112 provides 224 fine steps (7 * 32 = 234), resulting in a total of 992 fine steps.

Referring to Figure 4, an exemplary embodiment of circuitry to implement the DC restoration and slicer stages 104, 114 includes respective ones of a sheer circuit 204a/214a, a bias current source 204b/214b for coarse control, a bias current source 204c/214c (e.g., implemented as current DACs) for fine current control, and a lookup table (LUT) 204d/214d, all interconnected substantially as shown. As discussed above, the input signal 103/113 is DC- restored and sliced by the slicer circuit 204a/214a to provide the DC-restored and sliced signal 105/115. Amplitude control of the output signal 105/115 is achieved by controlling the coarse Ic and fine If bias currents in accordance with the coarse boost control signal 125 that addresses LUT current control data 205d 215d, and fine amplitude control signal 121. respectively. During low data rate equalization, the fine amplitude control signal 121 is held constant.

Referring to Figure 5, an exemplary embodiment of the adaptation stages 106, 116 includes band pass filters 206a/216a, 206b/216b, full wave rectification circuits 206c/216c, 206c/216d, signal summing circuitry 206e/216e, and integration circuitry 206f/216f,

interconnected substantially as shown. The input 103/113 and output 105/115 signals of the DC restoration and slicer stage 104/114 are filtered by respective band pass filters 206a/216a, 206b/216b. As discussed in more detail below, each filter 206a/216a, 206b/216b has multiple available bandwidths (e.g., two), one of which is selected in accordance with a bandwidth control signal 133/135. The filtered signals 207a/217a, 207b/217b are full-wave rectified by the rectification circuits 206c/216c, 206d/216d. The summing circuitry 206e/216e is used to find the difference between these rectified signals 207c/217c, 207d/217d, with the resulting difference signal 207e/217e being integrated by the integration circuitry 20617216f to provide the adaptation feedback signal 107/ 117.

Referring to Figure 6, in accordance with an alternative embodiment, the ordering of the subtraction and integration of the rectified signals 207c/217c, 207d/217d can be reversed, as shown, with the rectified signals 207c/217c, 207d/217d first being integrated and then subtracted to provide the adaptation feedback signals 107/117.

Referring to Figure 7, in accordance with a preferred embodiment, the circuitry of Figure 1 is implemented as differential circuitry with differential signals. Accordingly, the adaptation feedback signals 107, 117 include respective positive 107p, 117p and negative 107n, 117n signal phases which are converted by a differential-to-single-ended conversion circuit 302 when applied across an automatic equalization control (AEC) capacitance 304 to produce a single-ended adaptation feedback signal 107/117. The reset signal 123 controls resetting of the accumulated charge across the AEC capacitance 304 (discussed in more detail below).

Referring to Figure 8, an exemplary embodiment of the control stage 120 includes a multiplexor 220a and a finite state machine (FSM) 220b, interconnected substantially as shown. Depending upon whether the input signal 101 is identified by the rate detection signal 131 as having a high or low data rate, the multiplexor 220a selects either the high 107 or low 117 rate adaptation feedback signal as the signal 221a to be provided to the FSM 220b. In accordance with the selected adaptation feedback signal 221a, the a FSM 220b provides the amplitude control signal 121, reset signal 123 and equalizer boost control signals 125, 127, 129, and adaptation filter control signals 133, 135 (discussed in more detail below).

Referring to Figure 9, the finite state machine 220b operates in accordance with an algorithm 400 as follows. Following initialization 402, an optimal equalizer boost is digitally selected using a binary search 404. As is well known in the art, for N programmable equalizer boost settings, it will take log ₂ (N) search steps to find the optimal equalization boost. The state machine 202b controls the sequential resetting and integration of charge on the AEC capacitance 304 for each step in the binary search process and then updates the equalization boost, i.e., to be higher or lower. Following completion of the binary search 404, the algorithm transitions 405a to amplitude adjustment 406 with the lower bandwidths of the filters 206a, 216a, 206b, 216b in the adaptation stages 106, 116 selected. This lower bandwidth carries the amplitude information and a linear search is used for amplitude loop convergence while performing amplitude adjustment 406. The amplitudes of the output signals 105, 115 of the DC restoration and sheer stages 104, 114 are tuned to match the amplitudes of their respective equalized input signals 103, 113. This advantageously avoids the need of an AGC amplifier in the equalizer paths. The convergence of the amplitude loop is detected by a change in direction of the amplitude code 407, following which the state machine 220b transitions 407 to boost adjustment 408 and the higher bandwidths of the band pass filters 206a/216a, 206b/216b in the adaptation stages 106/116 are selected. The finite state machine 220b then begins linear equalization boost adjustment 408. A change in direction or timeout in the equalization boost loop causes the state machine 220b to transition back 409 to amplitude adjustment 406.

In accordance with an alternative embodiment, following completion of the binary search 404, the algorithm can instead first transition 405b to boost adjustment 408, with the higher bandwidths of the filters 206a, 216a, 206b, 216b in the adaptation stages 106, 116 selected.

Upon convergence, the average value of the voltage across the AEC capacitance 304 (Figure 7) will be zero for both amplitude (low bandwidth) and equalization boost (high bandwidth) frequency bands of the band pass filters 206a/216a, 206b/216b. The state machine 220b will toggle back and forth 407, 409 between adjacent amplitude and equalization boost settings that are finely spaced.

Referring to Figure 10, an exemplary embodiment of the equalizer circuits 202a, 202b, 202c, 202d, 212a of the high rate filter 102 and low rate filter 112 (Figures 2 and 3) include multiple stages of parallel-connected DC amplifiers 502 and AC amplifiers 504 for receiving the positive 101p/103p and negative 101n/103n phases of the differential input signal 101, and providing the positive 103p/l 13p and negative 103n/l 13n signal phases of the output signals 103/113 which have been equalized as discussed above. The amplifiers 502, 504 are biased from a power supply VCC through resistors having a value R. Both the DC 502 and AC 504 amplifiers use differentially coupled NPN bipolar junction transistors with emitter degeneration resistances having a value 14R and bias current sources as shown. (It should be noted that this circuitry of Figure 10 includes seven differential amplifiers stages, reflecting the seven stages used by the low rate equalizer circuit 212. For each of the high rate equalizer circuits, 202a, 202b, 202c, 202d, six amplifiers stages are used and the emitter degeneration resistances have a common value of 12R.) The AC amplifiers 504 also include tunable impedances Zl, Z2, Z3, Z4, Z5, Z6, Z7 (Zl -Z6 for the high rate equalizers), which are driven by the fine adjust voltage 203e/212b as discussed above (discussed in more detail below). The bias current sources of the AC amplifiers 504 are controlled in accordance with the thermometer code represented by the bits bl, b2, b3, b4, b5, b6, b7 (bits bl-b6 for the high rate equalizers) of the coarse control signals 125/129, while the bias current sources of the DC amplifiers 502 are driven by the inverses of such bits.

Referring to Figure 11, an exemplary embodiment 504a of the AC amplifiers 504 include a tunable impedance implemented as an impedance 310 coupled between N-type metal oxide field effect transistors (N-MOSFETs) Nl, N2, the gate electrodes of which are driven by the fine control voltage 203e/212b. With the transistors Nl, N2 operating in their linear operating regions, a fine boost vernier control is provided, with step-wise linearity (discussed in more detail below). The impedance 310 can be implemented as virtually any form of impedance, such as a combination of one or more additional resistances and one or more capacitances. In accordance with a preferred embodiment, the impedance 310 is implemented as a capacitance. As a result, in accordance with the thermometer-coded bits bn, the gain of the equalizer circuit 202a/202b/202c/202d/212a (Figure 10) will be as follows: bl b2 b3 b4 b5 b6 bl Gain

0 0 0 0 0 1

0 0 0 0 0 l+co*R*(Cl+C2)

1 0 0 0 0 l+a>*R*(Cl+C2+C3)

1 1 0 0 0 l+co*R*(Cl+C2+C3+C4)

1 1 1 0 0 1 +oo*R*(C 1 +C2+C3+C4+C5)

1 1 1 1 0 1 +co*R*(C 1 +C2+C3+C4+C5+C6)

1 1 1 1 1 1 +co*R*(C 1 +C2+C3+C4+C5+C6+C7) for Zn = l/(jco(0.5Cn) and n = number of stage

Referring to Figure 12, as discussed above, the thermometer coding of the fine adjust bits provide for a step-wise linear adjustment of the equalization, with each of these 32 fine steps providing a resolution of 0.08 dB between adjacent ones of the 768 coarse steps in the high rate filter 102 and 224 coarse steps in the low rate filter 112.

Referring to Figures 13 and 14, the timing of the adjustment of the fine control voltage and coarse tuning bits are preferably as indicated. For example, adjustment of the fine tuning voltage should only occur when the AC amplifiers 504 are enabled and the DC amplifiers 502 are disabled.

Referring to Figure 15, an exemplary embodiment of the rate detection stage 130 includes a high bandwidth band pass filter 230a, a low bandwidth band pass filter 230b, full wave rectification circuits 230c, 230d, a summing circuit 230e, and integration circuitry 230f, interconnected substantially as shown, similar to the adaptation stages 106, 116 (Figure 5). The high band pass filter 230a provides a filtered signal 231a indicative of signal energy in the high frequency band, while the low band pass filter 203b provides a filtered signal 23 lb indicative of energy in the low frequency band. These signals 231a, 231b are full-wave rectified by the rectification circuits 230c, 23 Od, and the rectified signals 231c, 23 Id are subtracted in the summing circuit 23 Oe to produce a signal 23 le indicating whether the high frequency band or low frequency band contains more energy. This signal 23 le is integrated by the integration circuitry 23 Of to produce the rate detection signal 131. (In accordance with an alternative embodiment, due to their similarities, with appropriate signal switching and routing within the equalizer 100, the rate detection stage 130 can be implemented by sharing filters, rectification circuits, summing circuitry and integration circuitry with one or both of the adaptation stages 106, 116.)

Based upon the foregoing discussion, it will be understood that changes in equalization boosts will have some effect on the low frequency band that is used for amplitude control and calibration. Conversely, changes in the amplitude of the sliced signals 105, 115 will have some effect on the energy in the high frequency boost adaptation. This effectively results in two interacting loops that can potentially diverge and cause the equalization adaptation to go out of lock or convergence. However, this is avoided by operation of the finite state machine 220b, which uses interlaced amplitude and equalization boost loop adaptation and allows for disabling of the amplitude calibration loop. Early saturation of the amplitude calibration can be implemented to freeze the amplitude calibration loop beyond a predetermined range.

Additionally, a programmable timeout from the amplitude and equalization boosts loops are different and separated in frequency. Further still, a programmable timeout from the amplitude and equalization boost loops are different and separated in frequency. Further still, a

programmable timeout from the amplitude and equalization boost loops is used in case there is no toggling between the two loops for a predetermined time interval. This also ensures that the loops do not remain stuck in a sub-optimal solution.

The embodiments discussed hereinabove have been designed for implementation by National Semiconductor Corporation as integrated circuits for low power adaptive cable equalization. Copies of the preliminary data sheets for two such implementations are included as part of this disclosure (and are hereby incorporated herein by reference) in the form of

Appendices A and B.

APPENDIX A

Na t io n a l PRELIMINARY

LMH0394 April 9, 2010

Semiconductor

3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer

General Description Features

© 2010 National Semiconductor ΟοφθΓβϋοη 301015 www.national.com

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Note 4: Specification is guaranteed by characterization. www.national.com

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Note 6: The differential output voltage and offset voltage are adjustable via the SPI.

Note 7: The equalizer automatically shifts equalization stages at cable lengths less than 240m (Belden 1694A) to reduce power consumption.

Note 8: Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in accordance with S PTE RP 184, S PTE RP 192, and the applicable serial data transmission standard: SMPTE 424M, SMPTE 292M, or SMPTE 259 .

Note 9: Input return loss is dependent on board design. The LMH0394 exceeds this specification on the SD394 evaluation board with a return loss network consisting of a 5.6 nH inductor in parallel with the 75Ω series resistor on the input.

Timing Diagrams

FIGURE 3. SPI Read

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CD

Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible

UJ

o o

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MUTE REFERENCE (MUTE _REF ) set high, the LMH0394 goes into a deep power save mode

The mute reference sets the threshold for CD and (with CD when no signal is detected. The device powers on again once tied to MUTE) determines the amount of cable to equalize an input signal is detected. The auto sleep functionality can before automatically muting the outputs. This is set by applybe turned off by setting AUTO SLEEP low or tying this pin to ing a voltage inversely proportional to the length of cable to ground. An additional auto sleep setting available in SPI mode equalize. The applied voltage must be greater than the can be used to force the equalizer to power down regardless MUTE _RFF floating voltage (typically TBD V) in order to change of whether there is an input signal or not. Auto sleep has the CD threshold. As the applied MUTE _REF voltage is inprecedence over mute and bypass modes.

creased, the amount of cable that can be equalized before www.national.com

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FIGURE . DC Output Interface to LMH0346 Reclocker

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input. After the SPI write, SS must return The prior SPI

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SPI Daisy-Chain Read followed by the read data for Device N-1 , Device N-2, etc.,

Figure 8 shows the SPI daisy-chain read for a daisy-chain of ending with the read data for Device 1 (the first device in the N devices. The SPI daisy-chain read is 32xN bits long, conchain). The 16-bit SPI read data for each device consists of sisting of 16xN bits for the read transaction followed by 16xN a "1" (read command), seven address bits, and eight "1"s bits for the dummy read transaction (aN "1"s) to shift out the (which are ignored). After the first 16xN bit transaction, SS read data on the MISO output. The SS signal is driven low must return high (to latch the data) and then is driven low and SCK is toggled for 16xN clocks. The first 16xN bit MOSI again before the second 16xN bit transaction of all "1 "s is sent payload (sent to Device 1 in the daisy-chain) consists of the to the MOSI input. The requested read data is shifted out on 16-bit SPI read data for Device N (the last device in the chain), MISO starting with the data for Device N _and ending with the data for Device 1. After this transaction, SS must return high. www.national.com

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,

10.

clock cycles.

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t

©

X R/W Addr Data R W Addr Data R W Addr Data R/W Addr Data

MOSI

1 0x7F 0x5A 1 0x7F 0x5A 1 0x7F 0x5A 1 0x7F 0x5A (host)

ISO

X XX XX X XX XX X XX XX 1 0x7F (host) ΡΧ5Λ

FIGURE 10. SPI Daisy-Chain Length Detection

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APPLICATION CIRCUIT (SPI MODE) ω

Figure 12 shows the application circuit for the L H0394 in

SPI mode.

component pads.

• Select trace widths that minimize the impedance

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For more National Semiconductor product information and proven design tools, visit the following Web sites at:

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can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders.

Copyright© 2010 National Semiconductor Corporation

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APPENDIX B

Na t io n a l ADVANCE

Semiconductor LMH0395 INFORMATION

February 26, 2010

3G HD/SD SDI Dual Output Low Power Extended Reach Adaptive Cable Equalizer

General Description Features

© 2010 National Semiconductor Corporation 301157 www.national.com

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LMH0395

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The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.

24-Pin LLP

Order Number LMH0395SQ

See NS Package Number SQA24A

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date Time: 2010/02/26 17:16:18 Block Diagram (Pin Mode)

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18 mode. The auto sleep functionality can be turned off by setting ential swing). This adjustable output common mode voltage

FIGURE 4. DC Output Interface to L H0346 Reclocker

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18

FIGURE 8. SPI Write Transaction Format

FIGURE 10. SPI Write Cascade Signal Timing

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18

(host)

"8X1 s" "1" '8X1 s" "1" "8X1 s" 16X1s' "16X1s" 6Χ Β"

MOSI

FIGURE 14. Chain Length Detection

A useful operation for the Host may be to detect the length of writes, the known data value will appear on the Host's MISO the daisy-chain. This is a simple matter of shifting in a series pin.

of NOP writes with a known data value (0x5A). After N+1 www.national.com

UNRELEEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18 Application Information X o ω

APPLICATION CIRCUIT (SPI MODE)

Figure 16 shows the application circuit for the LMH0395 in

SPI mode.

ground planes.

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date Time: 2010/02/26 17:16:18

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Daten ^' ime: 2010/02/26 17:16:18 Notes

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UNRELEASED COPY 301157 Version 1 Revision 31 Print Date/Time: 2010/02/26 17:16:18