Title:
ADDITION METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/097350
Kind Code:
A1
Abstract:
The present invention provides a summing circuit which suppresses overflow. The present invention is provided with a first memory, a second memory, a third memory, and a fourth memory. The present invention includes: a step in which items of signed first data are supplied to the first memory, and items of the first data that are saved in the first memory and have a positive sign are supplied to the second memory; a step in which items of the first data that are saved in the second memory and have a negative sign are supplied to the third memory; a step in which items of second data are generated by adding the items of first data saved in the second memory and having a positive sign to the items of first data saved in the third memory and having a negative sign; and a step in which the items of second data are saved in the fourth memory. When the items of second data saved in the fourth memory all have positive signs or all have negative signs, all of the items of second data saved in the fourth memory are added together.
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Inventors:
YAMAZAKI SHUNPEI (JP)
KIMURA HAJIME (JP)
FUKUTOME TAKAHIRO (JP)
KIMURA HAJIME (JP)
FUKUTOME TAKAHIRO (JP)
Application Number:
PCT/IB2018/058647
Publication Date:
May 23, 2019
Filing Date:
November 05, 2018
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
G06F7/499; G06G7/60
Foreign References:
| JP2003241958A | 2003-08-29 | |||
| JP2006277019A | 2006-10-12 | |||
| JP2002111447A | 2002-04-12 |
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