Title:
ADDRESS REFRESH CIRCUIT, METHOD, MEMORY, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/103148
Kind Code:
A1
Abstract:
An address refresh circuit (10), a method, a memory, and an electronic device. The address refresh circuit (10) comprises a selector circuit (101) and a decoding circuit (102); the selector circuit (101) is used for acquiring a gating signal, a redundancy address signal, and a normal address signal, and is used for selecting one of the redundancy address signal and the normal address signal as a target address signal on the basis of the gating signal respectively at a first pulse time and a second pulse time, the first pulse time and the second pulse time belonging to a same refresh cycle, and the second pulse time being later than the first pulse time; the decoding circuit (102) is used for decoding the target address signal to obtain and output a decoded signal.
Inventors:
CHEN JIXING (CN)
GAO ENPENG (CN)
GAO ENPENG (CN)
Application Number:
PCT/CN2022/072027
Publication Date:
June 15, 2023
Filing Date:
January 14, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/406
Foreign References:
| JPH11250694A | 1999-09-17 | |||
| CN104425003A | 2015-03-18 | |||
| CN110827884A | 2020-02-21 | |||
| US9805782B1 | 2017-10-31 | |||
| US20170352400A1 | 2017-12-07 | |||
| CN202111476366A | 2021-12-06 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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