Title:
ADHESIVE SHEET FOR SEMICONDUCTOR CONNECTING SUBSTRATE, ADHESIVE-BACKED TAPE FOR TAB, ADHESIVE-BACKED TAPE FOR WIRE-BONDING CONNECTION, SEMICONDUCTOR CONNECTING SUBSTRATE, AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/1997/030475
Kind Code:
A1
Abstract:
An adhesive sheet for semiconductor connecting substrate is a laminate which has an adhesive layer containing a thermosetting resin (A) and an epoxy resin (B), the epoxy resin (B) containing, as an essential component, at least one kind of epoxy selected from among (I) an epoxy resin having a dicyclopentadien skeleton, (II) an epoxy resin having a terpene skeleton, (III) an epoxy resin having a biphenyl skeleton, and (IV) an epoxy resin having a naphthalene skeleton. An adhesive-backed tape for TAB is a laminate which has an adhesive layer and a protective film layer both formed on a flexible insulating film, the softening temperature of the adhesive layer after curing being 60-100 �C and the insulation resistance dropping time of the layer when the layer is left after a DC voltage of 100 V is applied across the layer in an environment of 130 �C temperature and 85 % relative humidity being more than 50 hours. An adhesive-backed tape for wire-bonding connection is constituted of a laminate which has an adhesive layer and a protective layer both formed on a flexible insulating film, the softening temperature of the adhesive layer after curing being 120-170 �C, the storage elastic modulus D' at 150 �C of the adhesive layer being 20-100 MPa, and the insulation resistance dropping time of the layer when the layer is left after a DC voltage of 100 V is applied across the layer in the environment of 130 �C temperature and 85 % relative humidity being more than 50 hours. The adhesive sheet for semiconductor connecting substrate, adhesive-backed tape for TAB, and adhesive-backed tape for wire-bonding connection have excellent adhesive forces, insulating properties, dimensional accuracy, etc., and can improve the reliabilities of semiconductor integrated circuit connecting substrates and semiconductor devices.
Inventors:
SAWAMURA YASUSHI (JP)
KIGOSHI SHOJI (JP)
HATANO TAKU (JP)
KONISHI YUKITSUNA (JP)
ANDO YOSHIO (JP)
KIGOSHI SHOJI (JP)
HATANO TAKU (JP)
KONISHI YUKITSUNA (JP)
ANDO YOSHIO (JP)
Application Number:
PCT/JP1997/000453
Publication Date:
August 21, 1997
Filing Date:
February 19, 1997
Export Citation:
Assignee:
TORAY INDUSTRIES (JP)
SAWAMURA YASUSHI (JP)
KIGOSHI SHOJI (JP)
HATANO TAKU (JP)
KONISHI YUKITSUNA (JP)
ANDO YOSHIO (JP)
SAWAMURA YASUSHI (JP)
KIGOSHI SHOJI (JP)
HATANO TAKU (JP)
KONISHI YUKITSUNA (JP)
ANDO YOSHIO (JP)
International Classes:
C08G59/24; C09J7/22; C09J7/35; C09J163/00; H01L23/495; H01L23/498; C08L55/00; C08L77/00; (IPC1-7): H01L21/60
Foreign References:
| JPH08306744A | 1996-11-22 | |||
| JPH06338681A | 1994-12-06 | |||
| JPH06279739A | 1994-10-04 |
Other References:
See also references of EP 0823729A4
Download PDF: