BACKGROUND

The present disclosure, in some embodiments thereof, relates to an adjustable clock generator circuit to provide a clock signal and to minimize supply voltage to an integrated circuit (IC) or CPU core and, more specifically to an oscillator circuit with configurable delay paths, but not exclusively, to a specific oscillator circuit.

SUMMARY

It is an object of the present invention to provide an apparatus, a system, a computer program product, and a method that relates to an adjustable clock generator to minimize supply voltage to an integrated circuit or CPU core and, more specifically to an oscillator circuit with configurable delay paths, but not exclusively, to a specific oscillator circuit.

A clock generator circuit, comprising a gate having a first input electronically connected to an output of a first delay path circuit of another clock generator circuit and a second input electronically connected to an output of a second delay path circuit. An enabling circuit having at least one input electronically connected to an output of the gate. A latch circuit including a reset (R) having an input connected to an output of a third delay path circuit. A set (S) having an input connected to an output of the enabling circuit. An inverted Q output connected to an input of an inverter. An output of the inverter is connected to an input of the third delay path circuit. The output of the inverter provides a clock pulse output (cp) signal of the clock generator circuit. A Q output connected to an inverted input of the second delay path circuit. The gate performs an aggregation of the first input with the second input, to adjust a frequency of the clock pulse output (cp) signal responsive to the slowest delay path of the first path circuit or the second path circuit.

The enabling circuit may comprise an inverter including an enable input (en). An OR gate including an input connected to the reset (R) and another input from the output of the inverter. A NOR gate including an input from the output of the OR gate and the at least one input of the enabling circuit. The frequency of the clock signal output (cp) may be adjustable responsive to power supply perturbations in different locations of an integrated circuit. The gate may be a NAND gate. The first delay path circuit may be located in another area of the integrated circuit relative to the location of the second delay path circuit and the third delay path circuit. The outputs of the second and the third delay path circuits are decoupled at the reset and the set inputs of the latch to enable adjusting of the clock pulse output (cp) signal at every cycle of the frequency. The frequency of the clock pulse output (cp) signal may be reduced by a slowing operating unit in the integrated circuit. The frequency of the clock pulse output (cp) signal may be adjusted responsive to a user machine interface signal. The frequency of the clock pulse signal output (cp) signal may be reduced by a macro request of a slowing operating unit in the integrated circuit.

A method for establishing a frequency of a clock generator circuit, comprising a first output of a first delay path circuit of another clock generator circuit aggregated with a second output of a second delay path circuit of the clock generator circuit. The aggregating establishes the slower of delay of the first path delay circuit or the second delay path circuit. A frequency of the clock pulse output (cp) signal is adjusted responsive to the aggregating.

The first delay path circuit may be located in another area of the integrated circuit relative to the location of the second delay path circuit and a third delay path circuit of the clock generator circuit. The aggregating may be responsive to power supply perturbations in different locations of an integrated circuit. The second delay path circuit and the third delay path circuit of the clock generator circuit may be decoupled responsive to the adjusting of the frequency of the clock pulse output (cp) signal. Guard-banding of circuity may be enabled in different locations of the integrated circuit responsive to the adjusting of the frequency of the clock pulse output (cp) signal. The adjusting of the frequency of the clock pulse output (cp) signal may vary from one clock cycle to a next clock cycle of the clock pulse output (cp) signal, to facilitate frequency hopping and efficient speed debug of the integrated circuit. The frequency of the clock pulse output (cp) signal may be reduced when a slower operating unit in the integrated circuit is turned on.

The aggregating output of the first delay path circuit of another clock generator circuit with the second output of a second delay path circuit of the clock generator circuit may eliminate the sensing of multiple voltage-frequency V-F operation points in the integrated circuit by the clock generator circuit. Thereby, the clock generator circuit avoids switching between the voltagefrequency V-F operating points in the integrated circuit. The aggregating of the first delay path circuit of another clock generator circuit with the second output of a second delay path circuit of the clock generator circuit may be by logically NANDing the first output with the second output. The aggregating may obtain the slowest delay path from the first path circuit or the second path circuit.

According to an aspect, a process speed, voltage and temperature (PVT) responsive clock generator implemented at several locations across an IC macro to generate a momentary variable cycle time clock signal. The average frequency of the momentary variable cycle time clock signal is controlled to meet a target. The target is provided so that it does not exceed a previous calibration of the PVT clock generator in terms responsive to supply voltage, temperature and process dependent maximal operation frequency of the clocked macro of the IC. If the provided target exceeds error free operation cycle time, the PVT responsive clock generator will assert a signal to indicate so to the power supply controller of the IC. The power supply system should increase the supply to allow the PVT responsive clock generator to achieve the target and to never exceed the error free operation limit.

The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments of the disclosure, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Some embodiments of the disclosure are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments of the disclosure. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments of the disclosure may be practiced.

In the drawings:

FIG. 1 shows a combined circuit and block diagram of an oscillator 10 located in an integrated circuit (IC), in accordance with some embodiments;

FIG. 1A shows further details of a delay circuit, in accordance with some embodiments;

FIG. 2 shows a block diagram of an oscillator included an integrated circuit (IC), in accordance with some embodiments;

FIG. 2A shows further details of a half rate splitter circuit, in accordance with some embodiments;

FIG. 2B shows further details of a unit model, in accordance with some embodiments;

FIG. 2C shows a graph of frequency versus voltage curves for three configurable delay path units, in accordance with some embodiments;

FIG. 2D shows more details of a delay path circuit used to implement delay path units in each unit model shown in FIG. 2C.

FIG. 2E shows more details of a combiner circuit, in accordance with some embodiments; and

FIG. 3 shows a flow chart of a method in accordance with some embodiments.

DETAILED DESCRIPTION

The present disclosure, in some embodiments thereof, relates to an adjustable tunable clock generator to minimize supply voltage to an integrated circuit or CPU core and, more specifically to an oscillator circuit with configurable delay paths, but not exclusively, to a specific oscillator circuit.

Before explaining at least one embodiment of the disclosure in detail, it is to be understood that the disclosure is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. The disclosure is capable of other embodiments or of being practiced or carried out in various ways.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

The present disclosure may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

By way of introduction aspects of the disclosure below, describe an oscillator that utilizes multiple, configurable, distributed delay models located at various parts in an integrated circuit (IC). The distributed delay models may be provided from same oscillator circuits 10 located at various parts of the IC. The other delay models may be used under the control of a controller to sense the process, voltage and temperature (PVT) throughout the integrated circuit (IC). Further, to offer immediate (next cycle) response to supply perturbations and thus to have a potential to reduce required margins and improve power and performance of the IC. Decoupling of the set S and reset R paths of a latch included in the oscillator allows tuning at every cycle (at high or at low phases) of a clock pulse to offer agile operation in response to tuning from one cycle to the next which further opens speed debug opportunities. The delay paths of the oscillator may therefore, function as process monitors and as aging monitors. The distribution of delay models at various locations of the IC enables power supply detection throughout the IC to capture the voltage frequency (V-F) curve and to enable the calibration of delay paths of several voltage threshold (Vt) types. The distribution of the delay models and operation of the oscillator of the above features allows modelling of wire delays in the integrated circuit, to allow compensation of the cycle period for voltage drops on farther away sites in a macro of the IC and allows modelling of clock network effects and arbitrary logic behavior.

Reference is now made to FIG. 1, which shows a combined circuit and block diagram of an oscillator 10 located in an integrated circuit (IC), in accordance with some embodiments. Oscillator 10 is used to generate a clock pulse cp that may be used by other components in the integrated circuit (IC). Clock pulse cp is provided on the output of inverter gate 12 at node n2. The input to inverter 12 is provided from the output of latch 16 from the output of NOR gate G4. The output of delay circuit 12 connects to an input of OR gate G5 of enable circuit 18 and to the reset R of latch 16. An input enable signal En connects to the input of inverter gate II and the output of inverter gate II connects to a second input of OR gate G5. The output of OR gate G5 connects to the set S input of latch 16. Latch 16 is shown implemented using two NOR gates G3 and G4. Other types of gates may be utilized to implement latch 16. Reset R connects to an input of NOR gate G3, the other input of NOR gate G3 connects to node n2, node n2 connects to the output of NOR gate G4 and the input of inverter gate 12. The output of NOR gate G3 connects to an input of NOR gate G4 at node nl, the other input to NOR gate G4 is the set S input to latch 16. Node nl connects to the input of inverter 13. The output of inverter 13 connects to the input of delay circuit 14. The output of delay circuit 14 connects to an input of NAND gate G1 labeled as input I _P 2. The outputs of other delay circuits of the other tunable or configurable oscillators (not shown) included and located in different areas of the integrated circuit (IC) may be applied on inputs I _pi and I _P 3 of NAND gate Gl. The output of NAND gate G1 connects to an input of NOR gate G2 included in enable circuit 18. Input X of NOR gate G2 may allow for a further number of inputs I _P 4-I _P 7 from outputs of other delay circuits of other tunable or configurable oscillators 10 via NAND gate Gn. Where the other tunable or configurable oscillators 10 are included and located in different areas of the integrated circuit (IC). Reference is now made to FIG. 1A which shows further details of delay circuit 12, in accordance with some embodiments. Delay circuit 12 implemented as shown may also be used to implement delay circuit 14. By way of non-limiting example and for purposes of simplicity, delay circuit 12 includes a combination logic portion of four two input NAND gates and a flip-flop portion which includes four flip-flops. Any odd or even number of combinational logic gates and flip-flops may be used for the range of delay required. In the combination logic portion, input I connects to one input of NAND gate xdl3 and the other pin connects to clock CK. Output n3 of NAND gate xdl3 connects to one input of NAND gate xdl2. The other input of NAND gate xdl2 connects to configure input cfg 1. The Output n2 of NAND gate xdl2 connects to one input of NAND gate xdll. The other input of NAND gate xdll connects to clock CK. The output nl of NAND gate xdll connects to one input of NAND gate xdlO. The other input of NAND gate xdO connects to configure input cfgO. The output O of NAND gate xdlO provides the output of delay circuit 12. Table T1 shows the possible inputs on each of the two inputs cfgO and cfgl of each of the four flip-flops. The fourth flip-flop has inputs a and b on two respective inputs, similarly the third flip-flop inputs c and d, similarly the second flip-flop inputs e and f and similarly the first flip-flop inputs g and h.

Included in operation of oscillator 10, the output of latch 16 is inverted by inverter 12 and the output of inverter 12 is generated clock output cp supplied at node n2. Phase delay circuit 12 delays the rise of generated clock output cp to a rising edge applied to the “reset” R input of latch 16. The rise of generated clock output cp is tunable or configurable. Together with the latch 16, phase delay circuit 12 is effectively a “one shot” circuit that may only stay at a high state for a period of time. The period is determined by the process speed, voltage and temperature (PVT) characteristic as well as the configuration data of phase delay circuit 12.

Similarly, if phase delay circuit 14 is the same as phase delay circuit 12 and is controlled the same, phase delay circuit 14 delays the fall of the output of latch 16 in response to the reset R assertion by phase delay circuit 12 to a rising edge of the set S input of latch 16. Phase delay circuit 14 is therefore, another, equal delay, “one shot” circuit. The output of phase delay circuit 14 however, will only stay low for so long. The period for which the output of latch 16 stays low is determined by the delay of phase delay circuit 14. While phase delay circuits 12 and 14 are identically controlled by a controller (not shown), their delay may not be exactly equal due to supply variations throughout the cycle of operation of oscillator 10 and the IC, among other factors. The set S input of latch 16 is supplied by the output of enable circuit 18. The set S input of latch 16 is from NAND gate G2 that NORSs other delay circuit paths from phase delay circuits of the other delay elements may also be tunable or configurable before a runtime of the IC and controllable at a runtime of the IC. The phase delay circuits of other delay element may be similar to or are the same as delay element 12. The outputs of the delay circuits of the other tunable or configurable delay paths may be applied on inputs I _pi and I _P 3. The output of latch circuit 16 on node n2 is applied to input Ip2 via inverter 13 and delay circuit 14. Inputs I _p i, I _P 2 and I _P 3 are NANDed by NAND gate G2, so that the output of enable circuit 18 asserts a “set” S signal to latch 16, only when all of paths supplied on inputs I _p i, I _P 2 and I _P 3 have switched to one. A feature of NAND gate G2, therefore, is that it aggregates inputs I _p i, I _P 2 and I _P 3. The aggregation of inputs I _p i, I _P 2 and I _P 3 enable the frequency of the clock pulse output (cp) signal to be configured by being responsive to the slowest delay path of the other delay elements supplied on inputs I _p i, I _P 3, I _P 4 - I _P 7 and I _P 2 provided from delay circuit 14 of oscillator 10.

Under the control of a controller included in the IC, where IC may be a CPU or included in the CPU. The frequency of the clock pulse output (cp) signal of oscillator 10 may be reduced to cause a delay when a slower operating unit in the integrated circuit IC is turned on. The delay will grow if voltage drops, without any need for tuning of the phase delay circuits 12 and 14 or any of the phase delay paths at different location in the IC. Yet the user and/or operating system may request a different frequency. On the other hand, the CPU macro itself may request a momentary slowdown when a slow unit is turned on. A user may alter the clock pulse output (cp) signal responsive to a request of the user. The frequency of the clock pulse output (cp) signal may be reduced when a macro of the IC or CPU requests for a momentary turning on of a slow operating unit in the integrated circuit.

In general, and according to descriptions that follow, the variations in operation of oscillator 10 and other delay paths at various other locations in the IC, enable the other delay paths to serve as sensors or monitors in the IC. A feature of other delay paths at various other locations in the IC is that they can be configured to perform a specific sensing or monitoring function under the control of a controller included in the IC.

Reference is now made to FIG. 2, which shows a block diagram of an oscillator 10 included an integrated circuit (IC) 20, in accordance with some embodiments. For the purpose of the discussions which follow, integrated circuit (IC) 20 may be further included in a CPU core (not shown). Common to all the components in IC 20 is a controller 24 that includes control lines (shown by dotted lines) connected to oscillator 10, half rate splitter 26, and unit models 22a and 22b. Unit models 22a and 22b outputs connect to input I _pi of oscillator 10 via combiner 28. In general multiple inputs I _pi and I _pn are provided on oscillator 10. The outputs of unit models 22a and 22b are provided from the phase delay circuits of other delay paths included in unit models 22a and 22b. The other delay paths are at various location of IC 20. The other delay paths may be similar to or are the same as oscillator 10. Inputs to unit models 22a and 22b is from the output of half rate splitter 26. The input to half rate splitter 26 is from the clock pulse output (cp) signal of oscillator 10 via buffer B2.

Reference is now made to FIG. 2A, which shows further details of half rate splitter 26, in accordance with some embodiments. Half rate splitter 26 at its input includes clock pulse cp applied to one input of NAND gate G6 and the rising edge enable (En) input of D-type latch Fl. The D input of latch Fl receives an enable signal E. The Q output of latch Fl is applied to the other input of NAND gate G6, the input of inverter gate 15 and enable input of flip-flop F2. The output of NAND gate G6 (loc_cp) is applied to the rising edge input (cp) of flip-flop F2. The Q output of flip-flop F2 (loc_q) is fed back to the D input of flip-flop F2 via invertor 14, and to one input of AND gate G7 and an input of NOR gate G8. The other input of AND gate G7 connects to the Q output of latch F3. The D input of latch F3 connects to the input of inverter 15 and the Q output of latch Fl. The level enable (E) input of D-type latch F3 connects to clock pulse cp. The output of inverter 15 connect to the other input of NOR gate G8. Half rate splitter 26 provides two enable outputs enO and enl on respective outputs of AND gate G7 and NOR gate G8. Clock pulse cp is a pulse signal with PVT fixed width of approximately 50% duty cycle. Output of G6 goes to falling edge triggered flip-flop F2. The bubble at the cp input of flip-flop F2 indicates, “inverted”, or falling edge sensitivity and the bubble at the Q output of flip-flop F2 indicates the same.

Reference is now made to FIG. 2B, which shows further details of a unit model 22, in accordance with some embodiments. Unit model 22a or unit model 22b may be implemented as unit model 22 that includes a pulse generator circuit 30. Enable outputs enO and enl of half splitter circuit 26 may be applied to respective inputs of unit model 22a or unit model 22b when unit model 22a or unit model 22b are each implemented as unit model 22. Specifically, for unit model 22, pulse generator 30 includes an input connected to clock signal cp. Clock signal cp connects to the rising edge enable (En) inputs of latches LI and L2 and one input of NAND gate G9. Enable enO may be applied to the input of latch LI. The output of latch LI is connected to the input of latch L2 and a second input of NAND gate G9. The output of latch L2 is connected to the input of inverter gate 16 and the output of inverter gate 16 connects to a third input of NAND gate G9. The output of NAND gate G9 connects to the input of buffer 17 and the output of buffer gate 17 provides a pulse (pls) output that connects in parallel to the clock (elk) inputs of delay path units 34U, 34L and 34S. Tuning controls 32 from controller 214 may be provided on multiple latches L3. The multiple output of latches L3 connect to the configure (cfg) input of each of the delay path units 34U, 34L and 34S. The three outputs of each delay path units 34U, 34L and 34S connect to three respective inputs of NAND gate GIO.

Reference is now made to FIG. 2C that shows a graph 200 of frequency versus voltage curves for three tunable or configurable delay path units 34U, 34L and 34S, in accordance with some embodiments. The three tunable or configurable delay path units 34U, 34L and 34S may be included in either unit models 22a and 22b. Three scaling curves 341, 342 and 343 are shown for respective delay path units 34S, 34L and 34U for respective Standard Voltage Threshold (SVT), Low voltage Threshold (LVT) and Ultralow Voltage Threshold regions (ULVT). Arrows 341b, 342b and 343b indicate a low voltage failure point, a mid-voltage failure point and a high voltage failure point respectively. The voltage axis is marked at points 341a, 342a and 343a indicate the voltage levels of supply of a low performance power supply, a normal power supply and a high performance power supply respectively at various locations of the IC. Prior to a runtime of the IC, a test time enables the tuning or configuring of the three delay path units 34U, 34L and 34S. The three scaling curves 341 , 342 and 343 are utilized to tune the three tunable or configurable delay path units 34U, 34L and 34S. Included in the tuning and the subsequent runtime of the IC delay path units 34U, 34L and 34S are utilized to provide a monitor or sensing of the frequency and power supply levels for delay path units 34U, 34L and 34S located at various locations of the IC.

Unit models 22a and 22b each implemented as unit model 22 serve as additional cycling paths. The additional cycling paths delay a rising edge to a rising edge (R2R) of clock pulse cp. Unit models 22a and 22b delay the rising edge by each generating short negative pulse; pulse pls. Pulse pls is from each pulse generator circuit 30 included in unit model 22a and unit model 22b. The pulses pls quickly reset the outputs of the cycling paths to zero and each pulse pls then goes through tunable or configurable delay path units 34U, 34L and 34S. Going through delay path units 34U, 34L and 34S delays the trailing edge of the pulse pls (rising) and produces a rising edge. The rising edge is tuned at the test time that represents the latency of some location of the integrated circuit (IC). At the runtime of the IC, after tuning and Voltage threshold (Vt) gate constants derived from the test time have been loaded to controller 24, the average frequency of the clock pulse cp is monitored. The average frequency may be monitored by controller 24 counting clock pulses of clock pulse cp in a window compared with an external, slow, fixed frequency reference clock. Only one set of controls of controller 24 may be modified at a time in order to slow down a clock frequency of an oscillator that is too high, as oscillator 10 waits for the last path of either unit models 22a and 22b to rise. A criteria of slowing down a clock frequency is that at no time, may the clock period of a clock signal become shorter than what is defined by all the other paths set at the test time. The criteria will prevent the clock of a macro of IC 20 from ever running so fast as to functionally fail the macro of IC 20 or the clock of a macro of a CPU. In sum, the duration of each clock signal (cp) cycle is tunable or configurable in a unit model 22, and is process, voltage and temperature (PVT) responsive by virtue of tunable or configurable delay path units 34U, 34L and 34S in each unit model 22. The clock cycle duration is determined by the largest delay (longest) of the delay path units 34U, 34L and 34S located in various places on the clocked macro of the IC, Where each of the delay path units 34U, 34L and 34S being influenced by the average supply voltage at its vicinity, at the time of the clock cycle.

Reference is now made to FIG. 2D that shows more details of a delay path circuit 34 used to implement delay path units 34U, 34L and 34S in each unit model 22, in accordance with some embodiments. Clock pulse cp input to delay path circuit 34 is provided from pulse pls. Pulse pls, is from each pulse generator circuit 30 included in unit model 22a and unit model 22b for example. Input cfgOO to NAND gates G19 and G17 are the multiple output of latches L3 that connect to configure (cfg) input of each of the delay path units 34U, 34L and 34S. The output Z of multiplexor MX4 is the output of each delay path units 34U, 34L and 34S.

Clock pulse cp input connect into a series connected chain of inverters 110-117. The outputs of inverters 110-113 provide four inputs to multiplexor MX1 and the outputs of inverters 114-117 provide four inputs to multiplexor MX2. Each of multiplexors MX1 and MX2 are supplied with two respective select inputs SO and SI. The outputs of multiplexors MX1 and MX2 provide the two inputs to multiplexor MX3 that are selectable by select input S2. Select inputs SO, SI and S2 are provided from controller 24. Select inputs SO, SI and S2 under the control of controller 24, sets the intended delay of delay path 34. Select inputs SO, SI and S2, set the number of inversion delays added to the path. In binary code, SO being the least significant bit (LSB), binary 000 for S2, S 1 and SO respectively, means zero and nothing is added on top of the minimal overhead except the contribution from inverter II. Therefore, binary 000 sets the fastest delay for delay path 34. Binary 111 for S2, SI and SO, means seven further inversions are added from inverters II 1-117 and hence the slowest delay for delay path 34.

The output of multiplexor MX3 provides the select input to multiplexor MX4. Clock pulse cp input connects to the input of inverter 118, the output (ckb) of inverter 118 connect to one input of OR gate G18 and OR gate G16. The other input of OR gate G16 connect to select input SO and the other input of OR gate G18 connect s the output of NAND gate G17. The output of OR gate G16 connect to the input of NAND gate G17. The output of OR gate G18 connect to the input of NAND gate G19. Input cfgOO to the other respective inputs to NAND gates G19 and G17 are the multiple output of latches L3 that connect to configure (cfg) input of each of the delay path units 34U, 34L and 34S. The two inputs sOb and sObb to multiplexor MX4 are provided from NAND gate G17 and NAND gate G19 respectively. The output (z) of multiplexor MX4 is the output of each delay path units 34U, 34L and 34S.

In the operation delay path circuit 34, when clock pulse cp switches down from high (1) to low (0). Both inputs to the output multiplexor MX4 are driven to 0 quickly (one gate delay). Hence the output Z switches to zero (0) (it had been 1), irrespective of the select input of multiplexor MX4 provided from the output of multiplexor MX3. After some time of the clock pulse cp being zero (0), the value of the select node of multiplexor MX4 with SO being what it is, drives output Z of multiplexor MX4 to zero (0) anyway. When clock pulse cp switches from high (1) to low (0), nothing happens, except that a transition starts to propagate in the inverters 110-117 input chain (8 gates). One of the nodes provided at the outputs of inverters 110-117 to the inputs of multiplexors MX1 and MX2 are selected by select inputs SO, SI and S2 acting as three configuration bits. The values of the configuration bits do not change during operation, only during calibration of delay path circuit 34. Hence, when the transition gets to a certain point, the transition propagates out of multiplexor MX3 to the select input of multiplexor MX4 and switches the output Z high. The exact delay depends on how many gates had to be traversed until the signal arrives at a selected node in the series connection of inverters 110-117. The selectable three configuration bits therefore provide eight possibilities of delay. As the selected inputs to multiplexors MX1 and MX2 may be rising (an even number of gates) or falling (an odd number of gates), then an XOR gate will invert the falling edges to make the falling edges to rise and not change the polarity of the even selections. An objective is to keep the falling edges rising, since the objective is to get a configurable delay rising edge to CfgOO, if 0, forces both sOb and sObb to be high (Z is high) rendering this delay path circuit 34 not-active. The XOR gate is implemented by multiplexor MX4, the inputs sOb and sObb to multiplexor MX4 when clock pulse cp = 1, inputs sOb and sObb are either 0-1 or 1-0 depending on select input SO. The dependence on select input SO means that the output of MX3 in response to a rise of clock pulse cp will cause the output Z to rise. Had select input SO been assigned, the opposite value for the same clock pulse cp rise would have the other polarity. However, inputs sOb and sObb of multiplexor MX4 would have been reversed as well, yielding the same result of the rise of Z in response to rise of clock pulse cp. Only the delay that is dependent on how many gates traversed, until the signal arrives at a selected node in the series connection of inverters 110-117, would have been different.

Reference is now made to FIG. 2E which shows more details of combiner 28, in accordance with some embodiments. Clock route cp_rt commonly supplies the clock pulse (cp) input of flipflops F4, F5 and F8. Clock route cp_rt is provided from the clock pulse output (cp) signal of oscillator 10. Whereas, the clock signals from a clock tree of the IC may be supplied as local clocks signals to unit models 22 located at various parts of the IC. Multiple unit models 22 located at various parts of the IC is shown as multiple rising edge to rising edge (R2R) paths 230 shown in a dashed box . With respect to FIG. 2, inputs 220a and 220b to flip-flops F7 and F6 respectively may be provided from the outputs of unit model 22a and 22b respectively. Enable signal E is applied to the D input of flip-flop F4 from the controller 24.

It is the output of G10 that enables (E) Combiner 28. Enable signal E is inverted by inverter 19 and the output of inverter 19 is connected to the clock data (cd) inputs of flip-flops F4 and F5. Enable signal E is also connected to one input of AND gate Gi l. The other input of AND gate Gil connect to the Q output of flip-flop F4. The output of AND gate Gil connects to the other multiple rising edge (R2R) paths 230 and the D input of flip-flop F5. The Q output (uEbf) is inverted by inverter 18, to give inverted output uenb. Inverted output uenb is connected to an input of NOR gate G12. The other input of NOR gate G12 connects to the Q output rdtrst of flip-flop F8. The output of NOR gate G12 connects to the D input of flip-flop F8 and input rdyplsO of AND gate G13. The Q output rdyrst of flip-flop F8 connects to an input of AND gate G14. The other inputs of AND gates G13 and G14 connect to clock route cp_rt. The output rdyplsO of AND gate G13 connects to the clock data (cd) input of flip-flop F7. The output rdyplsl of AND gate G14 connects to the clock data (cd) input of flip-flop F6. Outputs rdyO and rdyl of the Q outputs of respective flip-flops F7 and F6 connect to the two inputs of OR gate G15. In the context of FIG.l and FIG. 2 the output of OR gate G15 provides input I _pi to NAND gate G1 of oscillator 10.

The D inputs of flip-flops F7 and F6 are connected to “1”, so that when clocked (falling edge, note the bubble on the cp inputs of flip-flops F7 and F6) the output Q asserts a “1”. The output Q asserting a “1” enables the next cycle rise at the centrally located oscillator (oscillator 10), which, in turn, resets the active one of flip-flops F6 or F7 via a pulse derived from clock route cp_rt.

In other words flip-flops F6 or F7 when clocked by a falling edge, coming from the output of the NAND gate of multiple rising edge (R2R) paths 230, the output pin Q of flip-flops F6 or F7 becomes 1. The output pin Q of flip-flops F6 or F7 will remain 1 until the FF is reset by a reset pulse rdyrstO or rdypls 1. After the reset, the Q output will be ‘ 0 again, waiting for the next fall of the NAND gate of multiple rising edge (R2R) paths 230. Essentially, flip-flops F6 or F7 maintain the information that the slowest path of one of the 3 inputs to the NAND gate of multiple rising edge (R2R) paths 230, that is dependent on the voltage at the locations of the paths. It may not be possible to tell upfront which path has completed its programmed delay and turned ‘1. The Unit central oscillator 10 now “agrees” for the main clock cp to rise again. However, clock route cp_rt will rise after all other oscillators 10 and their respective root path have “agreed”. So a flip-flop in in each combiner 28 will hold that data until the clock cp actually rises. That rise will generate a reset pulse that will clear the flip-flops F6 or F7 in all the other combiners 28. The clearing of the flip-flops in all the other combiners 28 is for even and for odd cycles (rdyO, rdyl). The clearing takes place once every two cycles while the cycle before and the one after are handled by the other flip-flop F6 or F7 in each combiner 28. The cp_rt is a pulse (positive) coming from the rising edge of the main clock cp. The E input comes from the controller 24 that chooses to enable each combiner 28, or not to enable each combiner 28.

Reference is now made to FIG. 3 that shows a flow chart of a method 300, in accordance with some embodiments. Prior to a run time step 301, as part of a manufacturing and testing process, a comprehensive test is run on the macro clocked by oscillator 10, while varying the controls of the tunable or configurable delay paths of unit models 22a and 22b. The controls of Unit models 22a and 22b outputs connect to inputs I _pi and I _P 3 of oscillator 10 are tuned such that the functional testing of the macro will pass successfully at fastest passable speed. The outputs of unit models 22a and 22b are provided from the phase delay circuits of other delay paths included in unit models 22a and 22b. The other delay paths located and connected at various locations in IC 20. A delay is reduced only as long as the test passes, meaning that the macro clocked by oscillator 10 functions correctly. Tunable or configurable delay paths that are too fast result in functional failures that are not allowed and tuning is reverted back to passing settings of the delay controls provided by controller 24. Details of how a delay path is tunable or configurable, is shown with respect to the details of delay circuit 12 shown in FIG. 1A by binary values of inputs a-h that may be chosen and in the details of unit model 22 shown in FIG. 2B. Passing settings of the delay controls is done at several voltage points in the IC, to tune thereby, delay paths built of different voltage threshold (Vt) gates. Where a threshold voltage is related to the gates speed and leakage grading. Passing settings of the delay controls in effect captures and protects the functionality of oscillator 10 throughout the operation supply voltage range of the IC.

The aggregation of inputs I _p i, I _P 2 and I _P 3 and the control constants obtained for controller 24 prior to step 301, during the manufacturing and testing process of IC20, enables the frequency of the clock signal output (cp) of oscillator 10 to be configured. Configuration of the clock pulse output (cp) signal of oscillator 10 being responsive to the slowest delay path of the oscillators and oscillator 10 supplied on inputs I _p i, I _P 2 and I _P 3. The duration of each clock pulse output cp cycle is tunable or configurable and is process, voltage and temperature (PVT) responsive. The clock cycle duration is determined by the largest delay (longest) of paths located in various places on the clocked macro each being influenced by the average supply voltage at its vicinity, at the time of the clock cycle.

At step 301, in a run time for a pretested, manufactured and calibrated oscillator 10 in IC20, a clock output cp of oscillator 10 is aggregated with outputs of unit models 22a and 22b. The clock output cp of oscillator 10 is further aggregated with the output of delay circuits 12 and 14 separately on their own or with the output of delay circuits 12 and 14. The choice of the aggregation of inputs I _p i, I _P 2 and I _P 3 may be done by controller 24 or by a macro of IC 20. In circuit terms, NAND gates G1 and Gn. perform aggregating step 301. Since oscillator 10 uses multiple, configurable, distributed delay models to sense the process voltage temperature (PVT), aggregating step 301 eliminates the need for sensing multiple voltage-frequency V-F operation points and switching between the voltage-frequency V-F operation points in IC 20.

Prior to a run time step 301 and during the run time, the average frequency is monitored and controlled by the control circuit (24). It counts how many clock (cp) cycles are generated during a time period that is defined by a configurable number of reference clock cycles. The reference clock is a slow, external, fixed frequency clock. As an example, a 2.5GHz target cp frequency with a reference clock of 25MHz means 100 cp cycles in each reference clock cycle. Hence, in a typical averaging period of 100 reference cycles one would require 10000 cp cycles. A larger number than that would prompt the control (24) to increase the tunable or configurable latency of delay circuits 12, 14, whereas a smaller number would prompt the controller (24) to reduce that delay of delay circuits 12, 14. A reasonable averaging period may be 1000, or 10000 reference clock cycles as well, with the expected cp cycles count scaled accordingly.

In step 303, a frequency of the clock pulse output (cp) signal is adjusted responsive to aggregating step 301, so that unit models 22a and 22b serve as additional cycling paths in that they delay a rising edge to a rising edge (R2R) of clock pulse cp. Since unit models 22a and 22b delay the rising edge by generating a short negative pulse. The short negative pulse quickly resets the output of the cycling paths to zero and the short negative pulse then goes through a set of tunable or configurable delay elements. The set of configurable delay element being provided by delay circuits 12 and 14 and the delay circuits of other delay paths included in unit models 22a and 22b. Going through a set of configurable delay elements delays the trailing edge of the short negative pulse (rising) and produces a rising edge. The rising edge is configured at a time that represents the latency of some location of the integrated circuit (IC). Therefore, the adjusting of the frequency of the clock output cp at step 303 is responsive to configuring of the frequency of the clock pulse output (cp) signal of oscillator 10 prior to step 301 and in the run time, to power supply perturbations in different locations of IC 20.

Configuring of the clock pulse output prior to step 301, may be further enabled by decoupling delay circuits 12 and 14 at the reset R input and the set S input of latch 16 to enable configuring of the clock pulse output (cp) signal at every cycle of the frequency. In the run time, the frequency of the clock pulse output (cp) signal of oscillator 10 may be reduced when a slower operating unit in the integrated circuit (IC) 20 is turned on to cause a delay. The delay will also grow if voltage drops, without any need for reconfiguring of the clock pulse output. Yet the user or the operating system may request a different frequency. On the other hand, the CPU macro itself may request a momentary slowdown when a slow unit is turned on. A user may alter the clock pulse output (cp) signal responsive to a request of the user. The frequency of the clock pulse output (cp) signal may be reduced when a macro of IC 20 requests for a momentary turning on of a slow operating unit in the integrated circuit 20. In the run time, a local voltage drop of the logic at each oscillator at various locations on IC 20 will cause a delayed rise at the outputs of unit models 22a and 22b to push the rise and protect the logic. Further, by not having a delay path modeling the logic of integrated circuit (IC) 20, will force additional margin or guard banding so that the logic will not fail even when such a local volt drop happens.

In sum, oscillator 10 utilizes multiple, configurable, distributed delay models in IC 20 to sense the process, voltage and temperature (PVT) throughout IC 20 and offers immediate (next cycle) response to supply perturbations and thus has a potential to reduce required margins and improve power and performance of IC 20. Decoupling the set S and reset R paths of latch 16 prior to step 301 allows configuring at every cycle (at high or at low phase) of the clock pulse cp to offer agile operation in response to tuning from one cycle to the next which further opens speed debug opportunities. In other words the fall time of clock pulse output signal cp is configured by a different path other than the cycle path and the rise path. Configuring by the different path enables the change of controls by controller 24 when the paths are not active, in each cycle. Therefore, prior to step 301, there is a configuration of the fall path after the fall and tune, and the rise path after the rise but before the fall of the fall path. The delay paths of oscillator 10 may therefore in run time of IC 20, function as process monitors and as aging monitors. The distribution of oscillators at various location of IC 20 enables power supply detection throughout IC 20 to capture the voltage frequency (V-F) curve and to enable the calibration of delay paths of several voltage threshold (Vt) types.

Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

As used herein the term “about” refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of" and "consisting essentially of".

The phrase "consisting essentially of" means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word “exemplary” is used herein to mean “serving as an example, instance or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments.

The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the disclosure may include a plurality of “optional” features unless such features conflict.

Throughout this application, various embodiments of this disclosure may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range. Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging/ranges between” a first indicate number and a second indicate number and “ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment of the disclosure. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

It is the intent of the applicant(s) that all publications, patents and patent applications referred to in this specification are to be incorporated in their entirety by reference into the specification, as if each individual publication, patent or patent application was specifically and individually noted when referenced that it is to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present invention. To the extent that section headings are used, they should not be construed as necessarily limiting. In addition, any priority document(s) of this application is/are hereby incorporated herein by reference in its/their entirety.