Title:
ADVANCED PROCESSOR ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO/2016/100142
Kind Code:
A3
Abstract:
The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises : 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
Inventors:
VORBACH MARTIN (DE)
Application Number:
PCT/US2015/065418
Publication Date:
August 25, 2016
Filing Date:
December 13, 2015
Export Citation:
Assignee:
HYPERION CORE INC (US)
VORBACH MARTIN (DE)
VORBACH MARTIN (DE)
International Classes:
G06F9/38
Foreign References:
| US5699537A | 1997-12-16 |
Attorney, Agent or Firm:
GAMBHIR, Ajay, K. et al. (180 N. La Salle Suite 370, Chicago IL, US)
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