Silicon semiconductor wafers are typically obtained by slicing a single crystal silicon ingot in a direction normal to the axis of the ingot to produce thin wafers, profiling the edges of the wafers, grinding or lapping the wafers to remove surface damage induced by the slicing process, chemically etching the wafers to remove mechanical damage produced by the prior shaping steps, and finally, chemically/mechanically polishing the edge, and at least one surface of each wafer with, for example, a colloidal silica slurry and a chemical etchant, to ensure that the wafers have highly flat, reflective and damage-free surfaces. The wafers are then typically cleaned and quality inspected prior to being packaged.

Prior to chemical etching, silicon semiconductor wafers typically exhibit surface and/or subsurface defects such as embedded particles and physical damage such as micro-cracks, fractures or stress imparted to the wafer by upstream processes such as lapping, grinding and edge profiling. These defects generally occur in the region extending from the surface of the wafer to at least about 2. 5 ßm or greater

below the surface of the wafer. To remove these defects, therefore at least 2. 5 um of stock are removed from the surface of the wafer using an acidic or alkaline etchant thus removing the embedded particles, contaminants, and physical damage contained in the layer of stock that was removed.

In general, alkaline etching solutions offer several benefits over acid etching solutions. For example, alkaline etching tends to produce wafers having more uniform and flat surfaces than wafers etched with acid etching solutions, using relatively simple etching equipment.

Additionally, alkaline etching solutions provide excellent protection for silicon against deposition of metals (other than iron), because the metals convert either to insoluble precipitates or soluble salts resulting in a surface with fewer contaminants.

In addition to improving the quality of the resulting wafer, alkaline etching processes are inherently more safe with lower cost than the acid processes. Gaseous byproducts from the alkaline etching process are non-toxic, whereas acid etchants, which typically include nitric acid, produce nitrous oxides (NOx) as a gaseous byproduct of the acid etching process. The NOxare toxic to the human body and tend to be very difficult and costly to remove from the effluent gas to avoid polluting the environment and to comply with environmental regulatory requirements. In addition, alkaline etching solutions tend to react with skin tissue less quickly than acid etching solutions, making accidental exposure to alkaline etching solutions less dangerous to operating personnel than acid etching solutions.

Alkaline etching solutions are not superior to acid etching solutions in every respect, however. Wafers

subjected to alkaline etching processes often exhibit irregularities on the wafer surface and edge, such as a faceted surface which is revealed as an increased surface roughness compared to wafers etched by acid etching processes. Surface roughness can be reduced in the subsequent polishing step ; the polishing time required to produce acceptable surfaces, however, greatly increases with increasing surface roughness. Additionally, some device manufacturers require the backside surface of the wafer to remain"as etched."Wafers etched with alkaline etching solutions produce wafers with"as etched"backside surfaces with unacceptable surface roughness characteristics. Accordingly, semiconductor manufacturers typically consider the surface roughness problems associated with alkaline etching solutions to outweigh the benefits of alkaline etching and thus use acid etching solutions.

One attempt to provide a process for manufacturing semiconductor wafers using an alkaline etching solution, was proposed in United States Patent No. 5, 494, 862. U. S.

Patent No. 5, 494, 862 discloses a process in which a concentrated solution of sodium or potassium hydroxide, such as a 45 % by weight solution of sodium hydroxide, is used to etch the wafer. The etched wafer subsequently exhibits the increased surface roughness caused by the alkaline etching as discussed above. To reduce the surface roughness caused by alkaline etching, U. S. Patent No.

5, 494, 862 requires a light backside polishing in addition to the standard practice of polishing the front side of the wafer, thus increasing both the complexity and cost of the overall process. Additionally, the increased surfaces roughness caused by the conventional alkaline etchant generally results in increases in the polishing time for

polishing the front surface and edge surface of the wafer thus reducing the throughput and increasing the cost of the overall process.

SUMMARY OF THE INVENTION Among the objects of the invention therefore, may be noted the provision of an alkaline etching solution ; a process for using said solution for producing uniformly etched wafers ; the provisions of an alkaline etching solution and process for etching in which the etched wafers have a reduced surface roughness compared to wafers etched with conventional alkaline etching solutions ; the provisions of an alkaline etching solution and process for etching with enhanced safety characteristics over acid etching ; the provision of an alkaline etching solution and process for etching which improves the throughput of subsequent polishing steps ; and the provision of an alkaline etching solution and process for etching which reduces the amount of toxic emissions and/or the cost of environmental controls.

Briefly therefore, the present invention is directed to a process for etching silicon semiconductor wafers wherein the wafers are subjected to an alkaline etching solution comprising about 25 to about 65 percent by weight base and about 0. 5 to about 10 percent by weight oxidizing agent wherein said base comprises a metal hydroxide and said oxidizing agent comprises hydrogen peroxide or ozone.

Other objects and features of this invention will be in part apparent and in part pointed out hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a bar chart showing the surface roughness of p-wafers as a function of etchant composition, as described in Example 1.

Fig. 2 is a bar chart showing the surface roughness of p+ wafers as a function of etchant composition, as described in Example 2.

Table 1 shows the effect of the present invention upon edge roughness and polishing time, as described in Example 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Surprisingly, a process for etching a silicon semiconductor wafer has been discovered wherein the wafer is subjected to an alkaline etching solution comprising a base and an oxidizing agent, which enables the enhanced benefits of alkaline etching while producing wafers with reduced surface roughness compared to wafers etched with conventional alkaline etching solutions.

The process of the present invention is designed to utilize an alkaline etching solution comprising a base and an oxidizing agent to remove at least about 2. 5/m of stock from the surface of the wafer thereby removing the surface and subsurface defects such as embedded particles and mechanical damage such as those imparted to the wafer during slicing, grinding and/or lapping process steps, such that the resulting wafer has a reduced degree of roughness over wafers etched with typical alkaline etching solutions.

Wafers produced with the etching solution of the present invention have a greater uniform flatness and reduced roughness after etching such that the subsequent polishing time is significantly reduced.

Alkaline solutions comprising a base and an oxidizing agent have been previously used as cleaning solutions,

wherein dilute alkaline hydroxides are used in combination with oxidizing agents to repeatedly oxidize the surface of the wafer producing a thin silicon dioxide layer which is then immediately etched from the surface by the alkaline component thus removing contaminants from the surface of the wafer. See, e. g. U. S. Patent No. 5, 489, 557 and Japanese Patent Application No. Hei 06-245281. However, such cleaning methods are only designed to clean the surface of the wafer, and generally remove less than 1/m and more typically remove less than about 100 nm of stock from the surface of the wafer. Moreover, the rate at which cleaning solutions remove stock from the surface of the wafer decreases rapidly such that cleaning solutions will not remove sufficient quantities of stock to eliminate the defects described above, even when left in contact with the cleaning solutions for extended periods of time. Thus, while cleaning solutions may result in some stock removal, the amount of stock removed is several orders of magnitude less than that required to remove the embedded particles, contaminants, and physical damage as discussed above. In contrast, the concentrations of the base and oxidizing agent in the alkaline etching solution of the present invention are such that the etching effects of the base are greater than the oxidation effects of the oxidizing agent with the net effect being the removal of stock from the surface of the wafer.

The process of the present invention employs as a starting material a silicon semiconductor wafer which has been sliced from a single crystal silicon ingot and further processed using conventional grinding apparatus to profile the peripheral edge of the wafer and to roughly improve the general flatness and parallelism of the front and back surfaces. Accordingly, the wafer may be sliced from the

ingot using any means known to persons skilled in the art, such as, for example, an internal diameter slicing apparatus or a wiresaw slicing apparatus. Additionally, once the wafer is sliced from the ingot, the peripheral edge of the wafer is preferably rounded to reduce the risk of wafer damage during further processing. The wafer is then subjected to a conventional grinding process to reduce the non-uniform damage caused by the slicing process and to improve the parallelism and flatness of the wafer. Such grinding processes are well known to persons skilled in the art. Typical grinding processes generally remove about 20 m to about 30 hum of stock from each surface to roughly improve flatness using, for example, a resin bond, 1200 to 6000 mesh wheel operating at about 2000 RPM to about 4000 RPM.

The silicon semiconductor wafer may have any conductivity type and resistivity which is appropriate for a semiconductor application. Additionally, the wafer may have any diameter and target thickness which is appropriate for a semiconductor application. For example, the diameter is generally at least about 100 mm and typically is 150 mm, 200 mm, 300 mm or greater and the thickness may be from about 475 to about 900 Hm or greater, with the thickness typically increasing with increasing diameter. The wafer may also have any crystal orientation. In general, however, the wafers have a <100> or <111> crystal orientation.

Having been sliced from the ingot and subjected to the mechanical shaping processes described above, the wafer typically exhibits surface and/or subsurface defects such as embedded particles and physical damage such as micro- cracks, fractures or stress imparted to the wafer by upstream processes such as lapping, grinding and edge

profiling. These defects generally occur in the region extending from the surface of the wafer to at least about 2. 5 ßm or greater below the surface of the wafer. In addition, the surface of the wafer generally has a surface roughness of at least about 50 nm to about 100 nm or greater. The surface roughness may be measured using any metrology device capable of measuring the surface roughness. Such devices are well known in the art. For example, the surface roughness may be measured using an MP 300 surface measurement device which is commercially available from Chapman Instruments (Rochester, NY) or other metrology devices such as an AFM microscope, a Nomarski microscope at 50X magnification, a Wyko-2D microscope equipped with a 10X magnification, or an optical interferometer.

The present invention uses an alkaline etching solution to remove sufficient amounts of stock, at least about 2. 5/m or greater, from the surface of the wafer such that the region containing the defects described above is removed. Additionally, the present invention may be used to eliminate any other surface or subsurface defects which can be eliminated by removing stock from the surface of the wafer, or simply to remove a desired amount of stock from the surface of the wafer.

In accordance with the present invention, therefore, the surface of the wafer is brought into contact with an etching solution for a sufficient time period to remove a desired quantity of stock from the surface of the wafer.

In a preferred embodiment, the wafer is immersed in an etching solution either individually, or concurrently with multiple wafers to remove a sufficient quantity of stock from the surface of the wafer such that the defects located in the region removed are eliminated. Although the precise

number of wafers etched in a single bath is not critically narrow, typically 25 wafers are etched at a time, wherein said wafers are held in a support and rotated during the etching process. The rate of rotation is not critically important, however it typically varies from about 5 to about 100 revolutions per minute. Alternatively, the surface of the wafer may be contacted with the etching solution by spin etching, wherein one surface of the wafer is placed on a rotatable chuck, and the etching solution is sprayed on the surface apposing the surface attached to the chuck, while the wafer is rotated at high speed. While not critically narrow, the rotation speed of the chucked wafer ranges from about 10 to about 1000 rotations per minute.

The etching solution comprises a base and an oxidizing agent wherein the base is comprised of a metal hydroxide such as sodium hydroxide or potassium hydroxide, and the oxidizing agent is comprised of hydrogen peroxide and/or ozone. Furthermore, the etching solution is about 25 to about 65 percent by weight base, more preferably about 45 to about 50 percent by weight base and about 0. 5 to about 10 percent by weight, preferably about 0. 6 to about 6 percent by weight, and most preferably about 0. 6 to about 3 percent by weight oxidizing agent. Furthermore, the purity of the base and oxidizing agent and subsequently the etching solution, while not critically narrow, should be at least sufficient for general semiconductor wafer processing. Preferably, the base and oxidizing agent comply with the purity profiles as set forth in the Semiconductor Equipment and Materials International standards (hereinafter SEMI standards). For example, electronics grade hydrogen peroxide and potassium hydroxide, that meet or exceed the SEMI base standards are commercially available under the trademark CleanRoom from

the Electronic Chemicals Division of Ashland Chemical Co.

(Columbus, OH).

The temperature of the etching solution affects the etch rate. For example, increases in temperature generally results in an increase in etch rate. However, the solubility of the oxidizing agent in the etching solution generally decreases with increasing temperature.

Therefore, it is preferred that the temperature of the etching solution is maintained at about 35°C to about 95°C, more preferably about 65 °C to about 95 °C and most preferably about 90°C.

The surface of the wafer remains in contact with the etching solution for about 1 to about 5 minutes or until the desired amount of stock is remove from the wafer. The wafer is then removed from the etching solution and immediately rinsed with deionized water. Alternatively, other rinsing solutions known in the art may be used in place of the deionized water. The etching solution may be reused to subsequently etch additional wafers.

Accordingly, additional quantities of metal hydroxide, water and/or oxidizing agent may be added to replace solution that is used up during the etching of previous wafers.

The amount of time the wafer remains in contact with the etching solution is generally determined based on the desired amount of silicon to be removed from the surface of the wafer. The amount of silicon to be removed is a function of the flatness of the incoming wafer, the amount of defects on the surface and subsurface of the wafer, the depth at which the defects occur beneath the surface of the wafer, and the desired characteristics of the finished wafer. In a preferred embodiment, greater than about 2. 5 Am, more preferably about 3 to about 10 ßm, and even more

preferably, about 3 to about 6/m of material is removed from each surface of the wafer.

The amount of stock actually removed can be determined by measuring the total thickness of the wafer prior to and after etching. Once the amount of stock removed is determined, for a given wafer at a given immersion time and etchant concentration, the time a subsequent wafer remains immersed may be varied to increase or decrease the amount of stock removed. Alternatively, the concentration of the etchant may be monitored wherein the reduction in the concentration of the etchant is directly related to the amount of material removed from the surface. Accordingly, the reduction in the concentration of the etchant may be used to predict the amount of stock removed. The etchant concentration may be measured by any means known to persons skilled in the art, and may be determined by, for example, inductively coupled plasma magnetic spectroscopy. Persons skilled in the art may utilize any means known in the art for determining the amount of stock removed without varying from the scope of the present invention.

The resulting wafer has reduced surface and subsurface defects wherein the embedded particles and physical defects located in the layer of silicon removed from the wafer have been eliminated, and the resulting wafer surfaces have a roughness ranging from about 1,000 to about 2800 Å as measured using a model MP 300 surface measurement devise.

After etching, the wafer is polished using conventional polishing techniques. The wafer having a reduced roughness compared to wafers etched with conventional alkaline etchants requires less time for subsequent edge and notch polishing steps. For example, in a preferred embodiment, after the wafer is etched by the

present invention, the edge and notch of the wafer is polished using a Speedfam EP 300 edge polishing apparatus which is commercially available from Speedfam Co.

(Kanagawa, Japan), wherein an abrasive pad such as a Suba4 abrasive pad which is commercially available from Rodel Co.

(Newark, Delaware) is attached to the surface of a drum which then rotates at approximately 600 to 1, 000 RPM and is applied to the edge of the wafer with a polishing pressure of about 1, 600 to about 2, 000 grams of force while applying a polishing slurry comprising a colloidal silica slurry and about 1 to about 3 % potassium hydroxide. The amount of time required to polish the edge of a standard 200 mm wafer etched by the present invention to a roughness of about 30 o to about 500 A is approximately 1. 5 to 2 minutes whereas the time required to polish wafers etched with conventional alkaline etchants is 3 to 4 minutes. The time required to polish the notch o the wafer etched by the present invention to a roughness of about 30 to about 500 Å is approximately 15 to 30 seconds whereas the time required for wafers etched with conventional alkaline etchants is 30 to 60 seconds. In addition, the amount of material removed from wafers etched by the present invention to achieve the desired roughness is about 3 to about 6 microns compared to 5 to 8 microns for wafers etched with conventional alkaline etchants. Thus both the yield and throughput of the edge/notch polishing processes are improved.

Additionally, the front and back surfaces of wafers etched by the present invention have a roughness of less than about 2800 Å, more preferably less than about 2500 Å, more preferably less than about 2000 Å and most preferably less than about 1500 Å compared to the front and back surfaces of wafers etched with conventional alkaline etchants which generally have a surface roughness of

greater than 2800 Å, more typically greater than 3000 Å and ma@ have a surface roughness of at least 4500 Å or greater.

Consequently, the polishing time for the front and back surface is less for wafers etched by the present invention than for wafers etched with conventional alkaline etchants.

For example, the front surface and optionally the back surface of the wafer are polished using a conventional polishing apparatus such as a 6 DZ polishing apparatus which is commercially available from Strasbaugh Co. (San Luis Obispo, California), wherein a polishing pad for example, a Suba polishing pad which is commercially available from Rodel Co. (Newark, Delaware) is applied at a polishing pressure of about 40 to about 65 psi to the surface of the wafer at a temperature of about 20 to about 35 °C, while the polishing table is rotated at a speed of about 80 to about 120 RPM during which time, an abrasive mixture comprising colloidal silica is added at a flow rate of about 40 to about 100 ml/min and an alkaline solution comprising, for example, about 1 to about 3 weight percent metal hydroxide wherein said metal hydroxide comprises potassium hydroxide and/or sodium hydroxide at a pH of approximately 9. 5 to 12 is added at a flow rate of about 120 to about 300 ml/min. The front and/or back surface are polished to a roughness of about 5 to about 20 Å, with a global thickness variation of less than about 1 micron and a local thickness variation of less than about 0. 2 micron.

The time required to polish the front or back surface of the wafer etched by the present invention is approximately 200 seconds whereas the time required to polish the front or back surface of a wafer etched by conventional alkaline etchants is approximately 300

seconds. Thus the throughput of the surface polishing process is improved.

The following examples will illustrate the invention.

EXAMPLE 1.

P-ground silicon wafers were immersed in an etchant containing 45 % by weight KOH and 0. 6 % by weight H202 at approximately 90°C. Additional, P-ground silicon wafers were immersed in an etchant containing only 45 % by weight KOH at approximately 90°C. The wafers etched in the etchant containing 45 % by weight KOH and 0. 6 % by weight H202 exhibited a significantly reduced surface roughness compared to wafers etched in a purely alkaline etchant.

Figure 1 shows the improvement in surface roughness when wafers are produced using the etchant of the present invention, as compared with a purely alkaline, 45 % by weight KOH etch, for an equivalent amount of stock removal.

EXAMPLE 2 P+ ground silicon wafers were immersed in an etchant containing 45 % by weight KOH and 0. 6 % by weight H202 at approximately 90°C. Additional, P+ ground silicon wafers were immersed in an etchant containing only 45 % by weight KOH at approximately 90°C. The wafers etched in the etchant containing 45 % by weight KOH and 0. 6 % by weight H202 exhibited a significantly reduced surface roughness compared to wafers etched in a purely alkaline etchant.

Figure 2 shows the improvement in surface roughness when wafers are produced using the etchant of the present invention, as compared with a purely alkaline, 45 % by weight KOH etch, for an equivalent amount of stock removal.

EXAMPLE 3

Silicon wafers were immersed in an etchant containing 45 % by weight KOH and 3 % by weight H202 at approximately 90°C. Additional silicon wafers were immersed in an etchant containing only 45 % by weight KOH at approximately 90°C.

The edge of the etched wafers was then inspected visually under a bright light, and measured for roughness. The results shown in Table 1, show the edge of the wafers etched using the etchant of the present invention, were shinny in appearance and less rough, as compared with wafers etched in a purely alkaline etchant.

After measuring the edge roughness, the wafers were edge polished to remove all damage on the edge of the wafers. The wafers etched, using the etchant of the present invention, required less edge polishing time to remove the damage on the edge of the wafer, as compared with wafers etched in a purely alkaline etchant as shown in Table 1.

In view of the above, it will be seen that the several objects of the invention are achieved. As various changes could be made in the above-described semiconductor substrate flattening process without departing from the scope of the invention, it is intended that all matters contained in the above description be interpreted as illustrative and not in a limiting sense. In addition, when introducing elements of the present invention or the preferred embodiment (s) thereof, the articles"a,""an," "the"and"said"are intended to mean that there are one or more of the elements. The terms"comprising,""including" and"having"are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Table 1 Edge appearance Time required to Alkaline Roughness under bright remove damage by edge etch method R. (nm) light polishing Standard 142. 53 dull At least 3 min 10 sec caustic Modified 68. 54 shinny lmin24sec-1 min 56 caustic sec