Title:
AMORPHIZED BARRIER LAYER FOR INTEGRATED CIRCUIT INTERCONNECTS
Document Type and Number:
WIPO Patent Application WO2002041391
Kind Code:
A3
Abstract:
An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate [200] with a semiconductor device. A dielectric layer [208] is on the semiconductor substrate [200] and has an opening provided therein. An amorphized barrier layer [226] lines the opening and a seed layer [228] is deposited to line the amorphized barrier layer [226]. A conductor core [230] fills the opening over the barrier layer [226] to form a conductor channel. The seed layer [228] is securely bonded to the amorphized barrier layer [226] and prevents electromigration along the surface between the seed and barrier layers [228, 226].
Inventors:
LOPATIN SERGEY D
NGO MINH VAN
TRAN MINH QUOC
NGO MINH VAN
TRAN MINH QUOC
Application Number:
PCT/US2001/031297
Publication Date:
January 09, 2003
Filing Date:
October 04, 2001
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC (US)
International Classes:
H01L21/768; H01L23/532; (IPC1-7): H01L21/768; H01L23/532
Foreign References:
| US5899740A | 1999-05-04 | |||
| US5882738A | 1999-03-16 | |||
| EP0949673A2 | 1999-10-13 | |||
| US5998870A | 1999-12-07 |
Other References:
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 03 30 March 2000 (2000-03-30)
PATENT ABSTRACTS OF JAPAN vol. 018, no. 141 (E - 1520) 9 March 1994 (1994-03-09)
PATENT ABSTRACTS OF JAPAN vol. 018, no. 141 (E - 1520) 9 March 1994 (1994-03-09)
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