Title:
AMPLIFICATION CIRCUIT, AMPLIFICATION CIRCUIT NOISE REDUCING METHOD AND PROGRAM THEREOF
Document Type and Number:
WIPO Patent Application WO/2008/032763
Kind Code:
A1
Abstract:
[PROBLEMS] To realize a CMOS low-noise amplification circuit which can reduce
a chip area and design time and can be easily digital-controlled from outside.
[MEANS FOR SOLVING PROBLEMS] The amplification circuit includes: an amplification
stage (12) for amplifying an input signal to a desired value; a sample hold circuit
(13) which samples the output signal from the amplification stage (12) by a sampling
frequency of the frequency band of the output signal multiplied by at lest two
so as to be converted into a discrete time signal; a moving average calculation
unit (15) which selects and outputs a particular frequency band from the discrete
time signal outputted from the sample hold circuit (13) by a moving average operation;
and a smoothing filter (17) which smoothes the output signal from the moving average
calculation unit (15) and feed it back to the input of the amplification stage
(12).
Inventors:
ISHIZAKI HARUYA (JP)
MIZUNO MASAYUKI (JP)
MIZUNO MASAYUKI (JP)
Application Number:
PCT/JP2007/067792
Publication Date:
March 20, 2008
Filing Date:
September 13, 2007
Export Citation:
Assignee:
NEC CORP (JP)
ISHIZAKI HARUYA (JP)
MIZUNO MASAYUKI (JP)
ISHIZAKI HARUYA (JP)
MIZUNO MASAYUKI (JP)
International Classes:
H03F1/26; H03H17/02
Foreign References:
| JPH07288485A | 1995-10-31 | |||
| JPH03286612A | 1991-12-17 | |||
| JP2001119365A | 2001-04-27 | |||
| JP2000114880A | 2000-04-21 |
Attorney, Agent or Firm:
TAKAHASHI, Isamu (Shinoda Bldg. 10-7, Higashi Kanda 1-chome, Chiyoda-k, Tokyo 31, JP)
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