Background to the Disclosure

Future wireless communication networks, and in particular fifth generation networks, will require a large capacity, and this will necessitate a large communication bandwidth. Consequently, receivers for use in such networks will be required to operate at high frequency with low noise and low power consumption. A key element of a receiver is a low noise amplifier (LNA), located between an antenna and a down-conversion mixer. Therefore, there is a requirement for an improved amplifier.

In "A 1 .2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-um CMOS", Jarkko Jussila and Pete Sivonen, IEEE Journal of Solid-State Circuits, Vol. 43, No. 3, March 2008 ("Jussila et al"), a noise-cancelling LNA is disclosed that employs a technique referred to as a current-to-voltage combiner. Figure 1 , which is reproduced from Jussila et al, illustrates a scheme in which output currents of common-gate (CG) and common- source (CS) field effect transistors (FETs) are converted to voltages, and the voltages are summed. Summary of the Preferred Embodiments

According to a first aspect there is provided an amplifier adapted for noise suppression, comprising:

a first input for receiving a first input signal and a second input for receiving a second input signal, the first and second input signals constituting a differential pair;

a first output for delivering a first output signal and a second output for delivering a second output signal, the first and second output signals constituting a differential pair; a first transistor having a first drain coupled to the first output such that all signal current, except parasitic losses, flowing through the first drain flows through the first output, and the first transistor further having a first source coupled to the first input; a second transistor having a second gate coupled to the first input, a second drain coupled to the second output such that all signal current, except parasitic losses, flowing through the second drain flows through the second output, and the second transistor further having a second source coupled to a first voltage rail;

a third transistor having a third gate coupled to the second input, a third drain coupled to the first output such that all signal current, except parasitic losses, flowing through the third drain flows through the first output, and the third transistor further having a third source coupled to the first voltage rail;

a fourth transistor having a fourth drain coupled to the second output such that all signal current, except parasitic losses, flowing through the fourth drain flows through the second output, and the fourth transistor further having a fourth source coupled to the second input;

a first load coupled between the first output and a second voltage rail;

a second load coupled between the second output and the second voltage rail ; a first inductive element coupled between the first input and a third voltage rail; and

a second inductive element coupled between the second input and the third voltage rail;

wherein transconductance of the first transistor is substantially equal to transconductance of the fourth transistor, within ±5%; and

wherein transconductance of the second transistor is substantially equal to transconductance of the third transistor, within ±5%.

The amplifier may, therefore, perform at least partial noise cancellation, also referred to herein as noise suppression, on a balanced, or differential, signal. The terms "noise cancellation" and "noise suppression", or more concisely "cancellation" and

"suppression", are used herein to apply to noise generated within the amplifier, and not to noise or distortion present in the first and second input signals applied at the first and second inputs. The noise may be cancelled by summing currents of the first and third transistors at the first output, and currents of the second and fourth transistors at the second output. The amplifier is advantageous in providing cancellation that can be independent of output impedance of the amplifier, the cancellation instead being dependent on the ratio of transconductance of the first and second transistors and on the ratio of transconductance of the third and fourth transistors. Consequently, the amplifier may provide improved flexibility when designing a receiving apparatus incorporating the amplifier, enabling a wide bandwidth and low power consumption. ln some embodiments, the first transistor may have a first gate coupled to a bias voltage rail and the fourth transistor may have a fourth gate coupled to the bias voltage rail. This feature enables a low complexity. In other embodiments, the first transistor may have a first gate coupled to the second input and the fourth transistor may have a fourth gate coupled to the first input. This feature enables reduced power consumption.

The transconductance of the first transistor may be equal to the transconductance of the fourth transistor, and the transconductance of the second transistor may be equal to the transconductance of the third transistor. This feature enables a higher degree of noise cancellation.

In some embodiments, the transconductance of the second transistor may be equal to the transconductance of the first transistor, and the transconductance of the third transistor may be equal to the transconductance of the fourth transistor. This feature enables a high degree of noise cancellation.

In other embodiments, the transconductance of the second transistor may exceed the transconductance of the first transistor and the transconductance of the third transistor may exceed the transconductance of the fourth transistor. This feature enables the amplifier to have a low noise factor.

For example, the transconductance of the second transistor may be less than five times the transconductance of the first transistor, and the transconductance of the third transistor may be less than five times the transconductance of the fourth transistor. This feature enables a wide bandwidth. In particular, the transconductance of the second transistor may be twice the transconductance of the first transistor, and the

transconductance of the third transistor may be twice the transconductance of the fourth transistor. This feature provides a useful trade-off between noise cancellation and a wide bandwidth. In other embodiments, the transconductance of the second transistor may be three times the transconductance of the first transistor, and the transconductance of the third transistor may be three times the transconductance of the fourth transistor. This feature provides another useful trade-off between noise cancellation and a wide bandwidth.

In a preferred embodiment, the transconductance of the first transistor may be

0.02 Siemens. This feature enables good matching to typical antennas.

According to a second aspect there is provided a receiving apparatus comprising the amplifier according to the first aspect.

The receiving apparatus may comprise a balun and a mixer, wherein the first input and the second input are coupled to a differential output of the balun, and the first output and the second output are coupled to a differential input of the mixer. In such a receiving apparatus the amplifier is arranged to function as a low noise amplifier (LNA).

The receiving apparatus may also comprise an antenna coupled to a single-ended input of the balun.

According to a third aspect, there is provided a wireless communication device comprising the receiving apparatus according to the second aspect.

Preferred embodiments are described, by way of example only, with reference to the accompanying drawings. Brief Description of the Drawings

Figure 1 is a schematic diagram of a prior art noise-cancelling low noise amplifier. Figure 2 is a schematic diagram of a first embodiment of an amplifier adapted for noise suppression.

Figure 3 is graph illustrating the noise contribution of elements.

Figure 4 is a schematic diagram of a second embodiment of an amplifier adapted for noise suppression.

Figure 5 is a block schematic diagram of a receiving apparatus.

Figure 6 is a block schematic diagram of a wireless communication device.

Detailed Description of Preferred Embodiments

Referring to Figure 2, an amplifier 1 00 adapted for noise suppression comprises a first input 1 02 for receiving a first input signal V| _N+ and a second input 104 for receiving a second input signal V| _N- . The first and second input signals V| _N+ , V| _N- constitute a balanced pair, or differential pair, also commonly known as a differential signal. Therefore, the second input signal V| _N- is equal to an inversion of the first input signal V| _N+ . The amplifier 100 has a first output 1 06 for delivering a first output signal Ι ₀ υτ+ and a second output 1 08 for delivering a second output signal Ιουτ- The first and second output signals Ι ₀ υτ+, Ιουτ- together form a balanced pair, or differential pair, being constituent signals of a differential output signal Ι ₀ υτ, and therefore the second output signal Ι ₀ υτ- is equal to an inversion of the first output signal Ι ₀ υτ+-

A first transistor M _C GI is arranged in a common-gate configuration, having a drain 1 10 coupled to the first output 1 06, a source 1 12 coupled to the first input 102, and a gate 1 14 coupled to a bias voltage rail 140 supplying a bias voltage V _B IAS- The drain 1 10, source 1 12 and gate 1 14 of the first transistor M _C GI alternatively may be referred to as, respectively, a first drain 1 10, a first source 1 12 and a first gate 1 14, for conciseness. The first drain 1 10 may be coupled directly to the first output 106, that is, without any intervening element having resistance, capacitance or inductance, apart from parasitic resistance, capacitance or inductance, or alternatively such an intervening element may be present. Nevertheless, the first drain 1 10 is coupled to the first output 106 such that that all signal current, except parasitic losses, flowing through the first drain 1 10 flows through the first output 106. The term "signal current" means current flowing due to either or both of the first input signal V| _N+ and the second input signal V| _N- , and excludes biasing current.

A second transistor M _C si is arranged in a common-source configuration, having a gate 1 16 coupled to the first input 102 by means of a first capacitive element Ci, a drain 1 18 coupled to the second output 108, and a source 120 coupled to a first voltage rail 122 supplying a first supply voltage V _G G, which may be at a ground potential. In other embodiments the first capacitor C-i may be omitted, with the gate 1 16 of the second transistor M _C si being coupled directly to the first input 102. The drain 1 18, source 120 and gate 1 16 of the second transistor M _C si may alternatively be referred to as, respectively, a second drain 1 18, a second source 120 and a second gate 1 16. The second drain 1 18 may be coupled directly to the second output 108, or alternatively an intervening element may be present. Nevertheless, the second drain 1 18 is coupled to the second output 108 such that all signal current, except parasitic losses, flowing through the second drain 1 18 flows through the second output 108.

A third transistor M _C s2, also arranged in a common-source configuration, has a gate 124 coupled to the second input 104 by means of a second capacitive element C ₂ , a drain 126 coupled to the first output 106, and a source 128 coupled to the first voltage rail 122. In other embodiments the second capacitor C ₂ may be omitted, with the gate 124 of the third transistor M _C s2 being coupled directly to the second input 104. The drain 126, source 128 and gate 124 of the third transistor M _C s2 may alternatively be referred to as, respectively, a third drain 126, a third source 128 and a third gate 124. The third drain 126 may be coupled directly to the first output 106, or alternatively an intervening element may be present. However, the third drain 126 is coupled to the first output 106 such that all signal current, except parasitic losses, flowing through the third drain 126 flows through the first output 106.

A fourth transistor M _C G2 arranged in a common-gate configuration has a drain 130 coupled to the second output 108, a source 132 coupled to the second input 104, and a gate 134 coupled to the bias voltage rail 140. The drain 130, source 132 and gate 134 of the fourth transistor M _C G2 may alternatively be referred to as, respectively, a fourth drain 130, a fourth source 132 and a fourth gate 134. The fourth drain 130 may be coupled directly to the second output 108, or alternatively an intervening element may be present. Nevertheless, the fourth drain 130 is coupled to the second output 108 such that all signal current, except parasitic losses, flowing through the fourth drain 130 flows through the second output 108.

A first load Z _L i is coupled between the first output 106 and a second voltage rail

136 supplying a second supply voltage V _DD . A second load Z _L 2 is coupled between the second output 108 and the second voltage rail 136. The first load Z _L i and the second load Z|_2 have equal impedance, denoted Z _L , which, as explained further below, may be selected to provide the amplifier 100 with optimum output impedance for matching to an external output device coupled to the first and second outputs 106, 108.

A first inductive element L-i is coupled between the first input 102 and a third voltage rail 138 supplying a third supply voltage V _S s, which may be the same as the first supply voltage V _G G- A second inductive element L ₂ is coupled between the second input 104 and the third voltage rail 138. The first inductive element L-iand the second inductive element L ₂ have equal inductance, denoted L. The first and second inductive elements L-i , l_2 may be selected to provide a low impedance direct current (DC) path to the third voltage rail 138, thereby maximising the voltage headroom available to the first and fourth transistors M _C GI , M _C G2, thereby enabling low voltage operation, and at a radio frequency (RF), their inductance L may be selected either to cancel parasitic capacitance, or to be sufficiently large that their contribution to input impedance of the amplifier 100 is small.

The fourth transistor M _C G2 may be a duplicate of the first transistor M _C GI - In particular, transconductance of the first transistor M _C GI, denoted g _m i , is preferably equal to transconductance of the fourth transistor M _C G, denoted g _m4 . However, in practice the transconductance g _m i of the first transistor M _C GI may be typically within ±5% of transconductance g _m4 of the fourth transistor M _C G- Similarly, the third transistor M _C s2 may be a duplicate of the second transistor M _C si - In particular, transconductance of the second transistor M _C si , denoted g _m2 , is preferably equal to transconductance of the third transistor M _C s2, denoted g _m3 . However, in practice the transconductance g _m2 of the second transistor M _C si may be typically within ±5% of the transconductance g _m 3 of the third transistor M _C s2-

Assuming that fourth transistor M _C G2 is a duplicate of the first transistor M _C GI, and that the third transistor M _C s2 is a duplicate of the second transistor M _C si , and therefore that gmi =gm ₄ =gm,cG and g _m 2=gm3=gm,cs, the input impedance Z| _N of each of the first and second inputs 102, 104 of the amplifier 100 can be expressed as

Z _IN = l/ _grnCG (1 ) The differential input impedance between the first and second inputs 102, 104 is therefore Z| _N = 2/g _{M C} G Typically, the single-ended input impedance Z| _N is required to be

50Ω, or the differential input impedance is required to be 100Ω, for optimum matching to an external input device, such as a passive balun for matching the first and second inputs 102, 104 of the amplifier 100 to an antenna without reflection of signals, in which case the transconductance g _m ,cG of the first and fourth transistors M _C GI , M _C G2 is arranged to be 0.02S (0.2 Siemens).

The differential voltage gain A of the amplifier 100 can be expressed as

A = 2 _9inCG (1 ₊ /?)Z _L (2) where /? = g _rnCS /g m,CG■

The noise factor F, also known as noise figure, of the amplifier 100 can be expressed as

,- „ , (/?-i) ² , 4/? , 8

F= 1 +——— V H — V H

(β + 1) ^{2 Υ} (β + Ι) ² * Α(β + 1) ₍₃₎

where γ is a parameter dependent on the technology used, and is typically considered to be 1 . By coupling the third drain 126 of the third transistor M _C s2 directly to the first output 106 such that all current, except parasitic losses, flowing through the third drain 126 flows through the first output 106, and the second drain 1 18 of the second transistor M _C si to the second output 130 such that all current, except parasitic losses, flowing through the second drain 1 18 flows through the second output 108, the currents at the first and second outputs 106, 108 are sensed. Assuming that V| _N+ =-V| _N- =V| _N , that the fourth transistor M _C G2 is a duplicate of the first transistor M _C GI, and that the third transistor M _C s2 is a duplicate of the second transistor M _C si, and therefore that Ιουτ+=-Ιουτ-=Ιουτ, the differential transconductance gain of the amplifier 100, can be expressed as

(4)

If β=1 , the noise of the common-gate first and fourth transistors M _C GI , M _C G2, which is represented by the second term in equation (3), is completely cancelled. This condition, therefore, may be considered to correspond to optimum cancellation. If β≠1 , noise cancellation takes place, but is partial, that is, incomplete or non-optimum.

Referring to Figure 3, there is plotted, as a function of β, from β=1 to β=4, and for γ=1 , g _m ,cG=0.02S and Z _L =500Q the noise contribution to the noise factor F of the amplifier 100 of, in curve (a), the first and fourth transistors M _C GI , M _C G2, in curve (b), the second and third transistors M _C si, M _C s2, and, in curve (c), the first and second loads Z|_1 , ZL2 in combination. The overall noise factor F, being the sum of these noise contributions, is plotted in curve (d). It can be seen from Figure 3 that the noise contribution of the first and fourth transistors M _C GI , M _C G2 increases for β>1 , that is, g _m ,cs ^> gm,cG- However, the noise contribution of the second and third transistors M _C si, M _C s2 and of the first and second loads Z _L i, Z _L2 decreases as β increases above unity, with the result that the total noise decreases as β increases from one to four. Moreover, by employing β> 1 for partial noise cancellation, it can be seen from equation (4) that the differential transconductance gain of the amplifier 1 00 is higher than if β= 1 for optimum noise cancellation. Therefore, by employing β> 1 the amplifier 100 has a lower noise and a higher gain than possible if the amplifier 100 is operated with β= 1 for optimum noise cancellation, whilst enabling the input impedance Z _!N to be selected for optimum matching. The use of a high value of β can reduce the bandwidth of the amplifier 1 00, so in some embodiments a trade-off between lower noise, higher gain and reduced bandwidth may be made by selecting β to be greater than unity but less than, for example, 2, 3 or 5.

Therefore, in the amplifier 100, the transconductance g _m 2 of the second transistor Mcsi may exceed the transconductance g _m i of the first transistor M _C GI and likewise the transconductance g _m 3 of the third transistor M _C s2 may exceed the transconductance g _m4 of the fourth transistor M _C G2- However, in some embodiments, the transconductance g _m 2 of the second transistor M _C si may be less than five times the transconductance g _m i of the first transistor M _C GI, and in particular may be twice, or three times, the transconductance g _m i of the first transistor M _C GI- Likewise, in some embodiments, the transconductance g _m 3 of the third transistor M _C s2 may be less than five times the transconductance g _m4 of the fourth transistor M _C G2, and in particular may be twice, or three times, the transconductance g _m4 of the fourth transistor M _C G2- In one preferred embodiment, the transconductance g _m1 of the first transistor M _CG i is 0.02S.

The impedance Z _L of the first and second loads Z _L i , Z _L2 impacts the absolute noise level in the amplifier 1 00, but has no impact on the noise cancellation, and therefore may be selected to be high to reduce the noise level, and to drive an external output device coupled to the first and second outputs 1 06, 1 08. Typically, such an external output device would be a mixer, and in particular a passive mixer, for down-converting an RF signal to baseband, and the matching should ensure a high bandwidth and a high linearity. The first and second loads Z _L i , Z _L 2 typically may be selected to provide very high impedance, for example at least 500Ω, and may be implemented, for example, using a current generator.

Referring to Figure 4, an alternative embodiment of the amplifier 1 00 adapted for noise suppression has a topology identical to the topology of the embodiment described with reference to Figure 2, except that instead of the first and fourth gates 1 14, 134 being coupled to the bias voltage rail 140, the first gate 1 14 is coupled to the second input 104, and the fourth gate 134 is coupled to the first input 102. Such cross-coupling of the first and fourth transistors M _C GI , M _C G2 can reduce the current required for providing a desired input impedance of the amplifier 100, thereby reducing power consumption, although this may increase capacitance at the first and second inputs 102, 104, thereby reducing bandwidth of the amplifier 100.

In the following paragraphs, some key differences in operation between the amplifier 100 disclosed herein and the noise-cancelling LNA illustrated in Figure 1 and disclosed by Jussila et al are described, in order to highlight advantages of the amplifier 100.

The amplifier 100 disclosed herein sums the current of the common-gate first transistor M _C GI and the common-source third transistor M _C s2 at the first output 106, and sums the current of the common-gate fourth transistor M _C G2 and the common-source second transistor M _C si at the second output 108. In contrast, referring to Figure 1 , a consequence of the different topology (compared with the amplifier 100 in Figure 2) of the load circuit comprising the impedances Z^ and Z ₂ and its coupling to common-gate and common-source transistors M _{1 P} and M ₂ p, and the corresponding topology for common- gate and common-source transistors M _N1 and M _N2 , is that output currents of the common- gate and common-source transistors M _{1 P} and M ₂ p, and M _N1 and M _N2 , are not summed at the outputs, but instead are summed at internal nodes of the load circuits, in particular at the junction between the impedances Z^ and Z ₂ on the left side of Figure 1 , and at the corresponding junction on the right side of Figure 1 .

The differential voltage gain of the noise-cancelling LNA of Figure 1 is

A'=2g _m1 (Z ₁ +Z ₂ ), and the differential transconductance gain is g _m i, where g _m i is the transconductance of the common-gate transistor M _{1 P} and of the common-gate transistor M _{1 N} . Typically, to assure input matching, an input impedance of 50Ω is required, which can be provided by selecting g _m1 =0.02S. By selecting high values for the impedances Z^ and Z ₂ , the differential voltage gain A' can be high and the noise contribution of the impedances Z^ and Z ₂ can be low, but the differential transconductance gain, equal to g _m1 , is constrained by the requirement for input matching. In contrast, as can be seen from equations (2) and (4), the differential voltage gain A and the differential transconductance gain IOUT/V| _N of the amplifier 100 can be increased due the presence of the parameter β in equations (2) and (4), and by increasing the parameter β. This design flexibility of the amplifier 100 simplifies the design of apparatus incorporating the amplifier 100.

In the noise-cancelling LNA of Figure 1 , because the noise cancellation takes place in the voltage domain, the degree of noise cancellation will be affected if the output of the LNA is loaded by being coupled to a low impedance device, for example a broadband passive current mixer. In contrast, in the amplifier 100 the first and second loads Z|_i , Z|_2 do not affect the noise cancellation of the amplifier 100, so may be freely selected for optimum output matching. Again, this design flexibility of the amplifier 100 simplifies the design of apparatus incorporating the amplifier 100.

The noise factor F' of the noise-cancelling LNA of Figure 1 may be expressed as γ 2 2 where β' is the ratio g _m 2 g _m i of transconductance g _m 2 of the common-source transistor M ₂ p to the transconductance g _m i of the common-gate transistor M _{1 P} . Likewise, β' is also the ratio of transconductance of the common-source transistor M ₂ N to the transconductance of the common-gate transistor M _{1 N} . Therefore, γ/β' in equation (5) is the noise of the common-source transistors M ₂ p, M _2N . For the purpose of comparison, it is herein assumed that β'=β. The term 2/A' represents the noise of the load impedance Z^+Z ₂ of the common-gate transistors M _{1 P} , M _{1 N} , and the term 2/Α'β' represents the noise of the load impedance Z ₂ of the common-source transistors M _2P , M _2N .

Referring to Figure 3, there is plotted, for the noise-cancelling LNA of Figure 1 , the noise contribution of the common-source transistors M _2P , M _2N in curve (e), the noise contribution of the load impedances Z^, Z ₂ in combination in curve (f), and the overall noise factor F', being the sum of these noise contributions, in curve (g), for differential voltage gain A'=20 and for y'=1 . The noise factor F of the amplifier 100 is higher than the noise factor F' of the noise-cancelling LNA of Figure 1 for values of β and β' exceeding about 1 .25, but the amplifier 100 has the advantages described above of greater design flexibility and higher differential transconductance gain.

Referring to Figure 5, a receiving apparatus 300 comprises an antenna 310 coupled to an input 322 of a receiver 320. An output 324 of the receiver 320 is coupled to an input 332 of a digital signal processor (DSP) 330. The receiver 320 comprises a balun 210 for converting a single ended received signal from the antenna 310 to the first and second input signals V| _N+ , V _!N- forming a differential, or balanced, signal. The receiver 320 also comprises the amplifier 100 for amplifying the first and second input signals V| _N+ , V| _N- , a mixer 220, a local oscillator signal generator (LO) 230, a filter 240, and an analogue to digital converter (ADC) 250. The balun 210 has an input 212 coupled to the input 322 of the receiver 320, and a differential output 214 for delivering the first and second input signals V| _N+ , V| _N- . The first and second input 102, 104 of the amplifier 100 are coupled to the output 214 of the balun 210. The first and second outputs 106, 108 of the amplifier 100 are coupled to a first differential input 222 of the mixer 220. Therefore, in the receiver 320 the amplifier 100 is arranged to operate as an LNA. The local oscillator signal generator (LO) 230 is coupled to a second input 224, which may be differential, of the mixer 220 for delivering a local oscillator signal. The mixer 220, which may be, for example, a passive mixer, down-converts the received signal after amplification by the amplifier 100, and delivers a down-converted signal at an output 226 of the mixer 220. The output 226 of the mixer 220 is coupled to an input 242 of the filter 240 for filtering the down-converted signal, and an output 244 of the filter 240 is coupled to the output 324 of the receiver 320 by means of the ADC 250. After digitisation of the down-converted and filtered signal in the ADC 250, the digitised signal is processed by the DSP 330 to extract information conveyed by the received signal.

Referring to Figure 6, a wireless communication apparatus 400 comprises the elements of the receiving apparatus 300 described with reference to Figure 5, and additionally comprises a transmitter 340 coupled between an output 334 of the DSP 330 and the antenna 310 for transmitting a signal generated by the DSP 330.

Although wireless communication has been used as an example, the invention also has application in other fields of communication, for example optical fibre

communication or communication via wire.

Other variations and modifications will be apparent to the skilled person. Such variations and modifications may involve equivalent and other features that are already known and which may be used instead of, or in addition to, features described herein.

Features that are described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, features that are described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

It should be noted that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single feature may fulfil the functions of several features recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims. It should also be noted that where a component is described as being "arranged to" or "adapted to" perform a particular function, it may be appropriate to consider the component as merely suitable "for" performing the function, depending on the context in which the component is being considered. Throughout the text, these terms are generally considered as

interchangeable, unless the particular context dictates otherwise. It should also be noted that the Figures are not necessarily to scale; emphasis instead generally being placed upon illustrating the principles of the present invention.