AMPLIFIER CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME

WIPO Patent Application WO/2008/023473

A1

During an initial setting interval, switches (21-23,71) are rendered conductive, so that the voltage of a signal line (SL) becomes equal to a power supply voltage (VSS) and that the input voltages of inverters (11-13) become equal to a logic threshold voltage. During a write interval, switches (51,61) are rendered conductive, so that the inverters (11-13) function as amplifiers. The inverter (13) in the final stage comprises a P-type transistor (14) and an N-type transistor (15) having a smaller current drive capability. At the beginning of the write interval, a current flowing through the P-type transistor (14) changes the voltage of the signal line (SL), so that even though the N-type transistor (15) has the smaller current drive capability, the change rate of the voltage of the signal line (SL) does not change. On the other hand, since the smaller current drive capability of the N-type transistor (15) causes the inverter (13) to have a larger output resistance, the frequency characteristic of an amplifier circuit (1) has an increased phase margin, resulting in a reduction of the power consumption of the amplifier circuit (1).

SHIMIZU, Shinsaku (())
清水 新策 (())

JP2007/056291

February 28, 2008

March 27, 2007

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SHARP KABUSHIKI KAISHA (22-22, Nagaike-cho Abeno-k, Osaka-shi Osaka 22, 5458522, JP)
シャープ株式会社 (〒22 大阪府大阪市阿倍野区長池町２２番２２号 Osaka, 5458522, JP)
SHIMIZU, Shinsaku (())

H03F1/34

SHIMADA, Akihiro (Shimada Patent Firm, Manseian Building 1-10-3, Yagi-ch, Kashihara-shi Nara 78, 6340078, JP)

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