Title:
AMPLIFIER CIRCUIT AND OPERATION METHOD THEREOF
Document Type and Number:
WIPO Patent Application WO/2014/088223
Kind Code:
A1
Abstract:
Disclosed is an amplifier circuit capable of achieving high efficiency at back off power while maintaining high output power when an amplifier of a driving stage is saturated in a multistage amplifier in which a plurality of amplifiers are connected in series to each other. In the amplifier circuit, at least two amplifiers including a first amplifier and a second amplifier, the first amplifier preceding the second the first amplifier, are connected in series to each other, the second amplifier changes input impedance according to output power from the first amplifier, and an impedance adjusting unit for adjusting output load impedance of the first amplifier is disposed between the first amplifier and the second amplifier, wherein the impedance adjusting unit optimizes the output load impedance of the first amplifier according to a change of input impedance of the second amplifier.
Inventors:
KIKUCHI HIROYOSHI (JP)
UEDA KAZUHIRO (JP)
UEDA KAZUHIRO (JP)
Application Number:
PCT/KR2013/010130
Publication Date:
June 12, 2014
Filing Date:
November 08, 2013
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD (KR)
International Classes:
H03F1/07; H03F3/60
Foreign References:
| US20120218044A1 | 2012-08-30 | |||
| JP2010050611A | 2010-03-04 | |||
| KR20110037033A | 2011-04-13 | |||
| US20060109053A1 | 2006-05-25 | |||
| US20080129410A1 | 2008-06-05 |
Attorney, Agent or Firm:
LEE, Keon-Joo et al. (Myongryun-dong 4-gaChongro-gu, Seoul 110-524, KR)
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