Title:
AMPLIFIER CIRCUIT AND RECEIVING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/142526
Kind Code:
A1
Abstract:
An amplifier circuit according to the present disclosure is provided with: a first transistor which has a drain that is connected to a first node; a second transistor which has a drain that is connected to a second node; a current source; a third transistor which has a gate that is connected to a third node, a source that is connected to the first node, and a drain that is connected to a power supply; a fourth transistor which has a gate that is connected to the third node, a source that is connected to the second node, and a drain that is connected to the power supply; and a plurality of circuits. Each one of the plurality of circuits comprises: a fifth transistor which has a gate that is connected to a fourth node and a source that is connected to the second node; a sixth transistor which has a gate that is connected to the fourth node and a source that is connected to the first node; and a resonant circuit which is inserted between the power supply and the drains of the fifth and sixth transistors.
Inventors:
YOSHIKAWA NAOTO (JP)
Application Number:
PCT/JP2018/044520
Publication Date:
July 25, 2019
Filing Date:
December 04, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03F3/191; H03F1/22; H03F3/45
Foreign References:
| JP2011518510A | 2011-06-23 | |||
| JPH09307378A | 1997-11-28 | |||
| US7091784B1 | 2006-08-15 | |||
| JP2012034191A | 2012-02-16 | |||
| US6509799B1 | 2003-01-21 | |||
| JP2015534420A | 2015-11-26 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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