Title

AMPLIFIER AND WIRELESS COMMUNICATION UNIT Technical Field

[0001] The technology relates to an amplifier and a wireless communication unit that are of high power and applicable to a wireless communication system.

Background Art

[0002] In recent years, a wireless communication system capable of transmitting and receiving large data amounts at high speeds has been in rapidly increasing demand due to the proliferation of smartphones. For instance, a new communication system such as LTE (Long Term Evolution) has entered a stage of practical use.

[0003] Further, due to worldwide globalization, the desire to globalize terminals and support a wide range of communication frequencies assigned to respective global regions has developed. Furthermore, since a smartphone may be equipped with many functions in a limited space, there has been a strong demand for small components.

[0004] To meet globalization as described above, a portable terminal capable of transmission and reception in various frequency bands drawn up in 3GPP (3rd Generation Partnership Project), as listed in Table 1, has been developed. [Table 1]

Examples of 3 GPP Band

Hi h fre uenc band

[0005] Further, a system using one power amplifier (PA) for each band has been developed to support the frequencies drawn up in 3 GPP. Citation List Patent Literature

[0006] PTL 1 : US Patent No. 7,773, 959B1 Summary

[0007] In this system, however, it is desired to increase the number of PAs as the number of bands increases, and to configure a terminal apparatus with a limited space accordingly. Additionally, smartphones, it is desired to support multiple bands and to increase a footprint.

[0008] To increase the footprint, a power amplifier circuit (an amplifier) as described in PTL 1 may be utilized. In this power amplifier circuit, however, the bandwidth is not broad enough, which is insufficient for desired bandwidth enhancements.

[0009] Thus, an amplifier and a wireless communication unit capable of realizing bandwidth enhancements to support an increase in the number of bands, and also achieving high efficiency and downsizing is desired.

[0010] For example, the amplifier comprises a set of field-effect transistors provided in series between a ground and an output load including, a first field-effect transistor with a source connected to the ground, a second field-effect transistor, and a first capacitor connected between a drain of the first field-effect transistor and a source the second first field-effect transistor, and a first device having a predetermined impedance value connected to a gate of the second field-effect transistor.

[0011] Further, the first device of the amplifier may be a capacitor. The predetermined impedance value may be responsive to a frequency of an input signal, and the predetermined impedance value may be determined by a voltage gain of the first field-effect transistor and an impedance of a gate capacitance in the second field-effect transistor. The first device of the amplifier may be a variable capacitor that may include a switch and a plurality of capacitors. The predetermined impedance value of the variable capacitor may be a variable impedance value that is responsive to the frequency of an input signal. The amplifier may further comprise a bias circuit separately connected to the gates of the first and second field-effect transistors via a first resistive element and a second resistive element, respectively. The amplifier may also further comprise a first stabilizing circuit connected between a gate of the first field-effect transistor and the gate of the second field-effect transistor.

[0012] Furthermore, the amplifier may comprise a third field-effect transistor included in the set of field-effect transistors; a second capacitor connected between a drain of the second field-effect transistor and a source the third first field-effect transistor; and a second device having a second predetermined impedance value connected to a gate of the third field-effect transistor. The second predetermined impedance value may be greater than the predetermined impedance of the first device when the first field-effect transistor, the second field-effect transistor, and the field-effect transistor are in the same dimension. The first device may be connected to an input node. The first device and the second device may be connected to an input node. The second device may be connected to an input node. The amplifier may further comprise a second stabilizing circuit connected between a gate of the first field-effect transistor and the gate of the third field-effect transistor. The amplifier may also further comprise a second stabilizing circuit connected between a gate of the first field-effect transistor and the gate of the third field-effect transistor.

[0013] Another example of the amplifier may include an amplifier that comprises a set of field-effect transistors provided in series between a ground and an output load including: a first field-effect transistor with a source connected to the ground, a second field-effect transistor, a first capacitor connected between a drain of the first field-effect transistor and a source the second first field-effect transistor, a third field-effect transistor included in the set of field-effect transistors, and a second capacitor connected between a drain of the second field-effect transistor and a source the third first field-effect transistor; a first device having a predetermined impedance value connected to a gate of the second field-effect transistor; and a second device having a second predetermined impedance value connected to a gate of the third field-effect transistor, wherein the predetermined impedance value is responsive to a frequency of an input signal.

[0014] Another example of the amplifier may include an amplifier that comprises a first field-effect transistor with a source connected to the ground, a second field-effect transistor, and a first capacitor connected between a drain of the first field-effect transistor and a source the second first field-effect transistor; and a first device having a predetermined impedance value connected to a gate of the second field-effect transistor.

[0015] Further, the predetermined impedance value may be determined by a voltage gain of the first field-effect transistor and an impedance of a gate capacitance in the second field-effect transistor. The amplifier may further comprise a third field-effect transistor included in the set of field-effect transistors; a second capacitor connected between a drain of the second field-effect transistor and a source the third first field-effect transistor; and a second device having a second predetermined impedance value connected to a gate of the third field-effect transistor. The second predetermined impedance value may be greater than the predetermined impedance of the first device when the first field-effect transistor, the second field-effect transistor, and the field-effect transistor are in the same dimension.

[0016] Accordingly, bandwidth enhancement supporting multiple bands and high efficiency and downsizing are achievable. Moreover, high efficiency may be realized in a maximum output state and in an output-reduced state.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. Brief Description of Drawings

[0018] FIG. 1 is a circuit diagram illustrating a configuration example of an amplifier according to a first embodiment;

FIG. 2 is a diagram illustrating a configuration example of an amplifier supporting a specified output power, by connecting FETs in parallel and synthesizing currents;

FIG. 3 is a diagram illustrating a circuit configuration example in which matching circuits are arranged in multiple stages so as to realize bandwidth enhancement;

FIG. 4 is an illustration indicating actual values when a simple matching circuit was arranged in an output stage, PAs were configured in two stages, and a WCDMA signal was input;

FIG. 5 is a circuit diagram illustrating a configuration example of an amplifier according to a second embodiment;

FIG 6 is a circuit diagram illustrating a configuration example of an amplifier according to a third embodiment;

FIG. 7 is a circuit diagram illustrating a configuration example of an amplifier according to a fourth embodiment;

FIG. 8 is a circuit diagram illustrating a configuration example of an amplifier according to a fifth embodiment;

FIG. 9 is a circuit diagram illustrating a configuration example of an amplifier according to a sixth embodiment;

FIG. 10 is a circuit diagram illustrating a configuration example of an amplifier according to a seventh embodiment;

FIG. 11 is a circuit diagram illustrating a configuration example of an amplifier according to an eighth embodiment;

FIG. 12 is a circuit diagram illustrating a configuration example of an amplifier according to a ninth embodiment;

FIG. 13 is a diagram illustrating configuration example of a wireless communication unit according to a tenth embodiment;

FIG. 14 is a circuit diagram illustrating a configuration example of an amplifier according to an eleventh embodiment;

FIG. 15 is a circuit diagram illustrating a circuit configuration of a major part of the amplifier illustrated in FIG. 14;

FIG. 16 is a circuit diagram illustrating a high-frequency equivalent circuit of the circuit illustrated in FIG. 15;

FIG. 17 is a schematic diagram illustrating one operation of the high-frequency equivalent circuit illustrated in FIG. 16;

FIG. 18 is a circuit diagram illustrating a configuration example of an amplifier according to a modification of the eleventh embodiment;

FIG. 19 is a circuit diagram illustrating a configuration example of an amplifier according to another modification of the eleventh embodiment;

FIG. 20 is a circuit diagram illustrating a configuration example of an amplifier according to yet another modification of the eleventh embodiment;

FIG. 21 is a circuit diagram illustrating a configuration example of an amplifier according to yet another modification of the eleventh embodiment;

FIG. 22 is a circuit diagram illustrating a configuration example of an amplifier according to yet another modification of the eleventh embodiment; FIG. 23 is a circuit diagram illustrating a configuration example of an amplifier according to yet another modification of the eleventh embodiment;

FIG. 24 is a circuit diagram illustrating a configuration example of an amplifier according to yet another modification of the eleventh embodiment;

FIG. 25 is a circuit diagram illustrating a configuration example of an amplifier according to a twelfth embodiment;

FIG. 26 is a circuit diagram illustrating a configuration example of an amplifier according to a modification of the twelfth embodiment;

FIG. 27 is a circuit diagram illustrating a configuration example of an amplifier according to another modification of the twelfth embodiment; and

FIG. 28 is a circuit diagram illustrating a configuration example of an amplifier according to yet another modification of the twelfth embodiment.

Description of Embodiments

[0019] Some embodiments of the technology will be described with reference to the drawings. It is to be noted that the description will be provided in the following order:

1. First embodiment (a first configuration example of an amplifier)

2. Second embodiment (a second configuration example of an amplifier)

3. Third embodiment (a third configuration example of an amplifier)

4. Fourth embodiment (a fourth configuration example of an amplifier)

5. Fifth embodiment (a fifth configuration example of an amplifier)

6. Sixth embodiment (a sixth configuration example of an amplifier)

7. Seventh embodiment (a seventh configuration example of an amplifier)

8. Eighth embodiment (an eighth configuration example of an amplifier) 9. Ninth embodiment (a ninth configuration example of an amplifier)

10. Tenth embodiment (a configuration example of a wireless communication unit)

11. Eleventh embodiment (a tenth configuration example of an amplifier)

12. Twelfth embodiment (an eleventh configuration example of an amplifier)

[1. First Embodiment]

[0020] FIG. 1 is a circuit diagram illustrating a configuration example of an amplifier according to the first embodiment.

[0021] An amplifier 100 has a first field-effect transistor (FET) 101, a second FET 102, a third FET 103, a first capacitor (capacity) 104, a second capacitor 105, an input terminal 106 for a RF signal, and a matching circuit 107, as illustrated in FIG. 1. The amplifier 100 has bias supply circuits (bias devices) 108 to 112, power sources 113 to 115, capacitors 116 to 118 serving as isolation devices, a bias circuit 119, and resistive devices 120 to 122 serving as bias devices. Further, a reference numeral 123 denotes an output load.

[0022] In the amplifier 100, a source of the first FET 101 is grounded, and a drain thereof is led to a source of the second FET 102 through the first capacitor 104. A drain of the second FET 102 is led to a source of the third FET 103 through the second capacitor 105. A drain of the third FET 103 is led to the load 123 through the matching circuit 107. Gates of the first FET 101, the second FET 102, and the third FET 103 are led to the input terminal 106, through an input node NDI and the capacitors 116 to 118, or directly.

[0023] The drain of the first FET 101 is led to the power source (or a power circuit) 113, through the bias supply circuit 108 formed of an inductor, a quarter- wavelength circuit, and the like. The source of the second FET 102 is grounded (connected to a ground potential), through the bias supply circuit 109 formed of an inductor, a quarter- wavelength circuit, and the like. The drain of the second FET 102 is led to the power source (or a power circuit) 114, through the bias supply circuit 110 formed of an inductor, a quarter- wavelength circuit, and the like. The source of the third FET 103 is grounded (connected to a ground potential), through the bias supply circuit 111 formed of an inductor, a quarter-wavelength circuit, and the like. The drain of the third FET 103 is led to the power source (or a power circuit) 115, through the bias supply circuit 112 formed of an inductor, a quarter- wave circuit, and the like.

[0024] The gates of the first FET 101, the second FET 102, and the third FET 103 are led to the bias circuit 119, through the resistive devices 120 to 122, respectively. The resistive devices 120 to 122 each function as the bias device, and may be formed, for example, of an inductor.

[0025] In general, a FET used for a power amplifier (PA) may be under a condition of being driven by a battery of about 3.5 V. Thus, to achieve a high output with a limited voltage, FETs are connected in parallel and currents are synthesized to achieve a specified output power as illustrated in FIG. 2. In contrast, the amplifier 100 according to one embodiment of the technology achieves a high output by synthesizing voltage signals, instead of synthesizing current signals.

[0026] A power supply voltage is limited by a battery voltage. When an attempt to obtain a specified output is made, an output impedance of the FET takes on an extremely low value of 5 Ω or lower in a case of current synthesis. As a result, when an attempt is made to perform matching to a system impedance of 50 Ω currently used in general, an extremely large conversion rate may be utilized. When an attempt is made to realize a matching circuit having a large conversion rate with a simple matching circuit, a Q value increases, and a band becomes narrow. To realize bandwidth enhancement, besides a matching circuit MTC, multiple stages thereof as illustrated in FIG. 3 may be utilized, resulting in enlargement of footprint and an increase in matching loss.

[0027] In example embodiments of the technology, in contrast, voltage synthesis is performed instead of current synthesis. In a case of the same output, a gate width of the FET may be one-third, which may realize a threefold output impedance of each of the FETs, and further, nine-fold impedances may be realized by providing them in three stages. An output impedance of the FET, which is 5 Ω or less in the current synthesis, may be increased to about 45 Ω. An impedance conversion rate to the system impedance 50 Ω is small even in a simple matching circuit and thus, there is no increase in Q value, making it possible to realize wideband characteristics.

[0028] FIG. 4 is an illustration indicating actual values when a simple matching circuit was arranged in an output stage, PAs were configured in two stages, and a WCDMA signal was input. In all the bands of 1 GHz or less drawn up in the 3 GPP specification, 40% efficiency was realized on a condition of ACLR < -38 dBc, and characteristics standing comparison with a single band PA were obtained.

[0029] It is to be noted that there is a related art (Japanese Unexamined Patent Application Publication No. 2008-236354), which proposes that FETs corresponding to the FET 102 and the FET 103 in FIG. 1 are grounded and cascode-connected. However, example embodiments of the technology are unquestionably different in that signals are input into the FET 102 and the FET 103. If the FET 102 and the FET 103 are cascode-connected, the FET 102 and the FET 103 only make additions to a voltage signal outputted from the FET 101 even in an ideal condition. As a result, only a gain of 3 dB may be obtained in each of the FETs at the maximum, and the gain falls on an actual device due to occurrence of a loss.

[0030] In contrast, in the amplifier 100 of one embodiment of the technology, signals are input together from the input into the gates of the first FET 101, the second FET 102, and the third FET 103. For this reason, the first FET 101, the second FET 102, and the third FET 103 each act as an amplifier and thus, a high gain as the amplifier may be provided.

[0031] It is to be noted that a high gain may be obtainable even with the configuration according to the related art discussed above, when a device having a predetermined impedance at a frequency of an input signal is provided for the gate of the FET 102 and for the gate of the FET 103 as described later.

[0032] Meanwhile, a system of adjusting an output power based on a distance from a base station has been adopted in portable-telephone communications. In a PA for a portable telephone, optimization in maximum output state may be performed to meet a radio-wave specification in the maximum output state, but electrical efficiency deteriorates in a region where the output falls. To address this issue, efficiency in a low output state is increased by adjusting a gate bias or making an adjustment to a drain voltage with a DC-DC converter. However, due to mounting of the DC-DC converter, there are issues such as enlargement of a footprint and an increase in cost. Further, there is a system that improves efficiency by deriving an output of a PA from the preceding stage. However, only use with an output power of about 10 dB lower than the output power in the maximum output state is possible. In a new communication system such as LTE, a frequency of use with output power, which is about 3 dB to 5 dB lower than the output power in the maximum output state, is high. Therefore, there is a demand for improvement in efficiency with 10-dB lower output and efficiency with 3-dB lower output. A configuration meeting this demand will be described below as the second embodiment.

[2. Second Embodiment]

[0033] FIG. 5 is a diagram illustrating a configuration example of an amplifier according to the second embodiment.

[0034] An amplifier 100A according to the second embodiment is different from the amplifier 100 according to the first embodiment, as follows. In this amplifier 100A, the drain of the first FET 101 and the drain of the second FET 102 may connected using a switch 124 such as an FET switch, and the drain of the second FET 102 and the drain of the third FET 103 may be connected using a switch 125.

[0035] In the amplifier 100A, in the maximum output state, for instance, the first FET 101, the second FET 102, and the third FET 103 function as amplifiers by using the switches 124 and 125 in an OFF state. In medium output state, it is possible to perform amplification without using the third FET 103, by applying a gate voltage to set the third FET 103 in an OFF state, and further, by setting the switch 125 in an ON state. Furthermore, it is possible to derive an output of the second FET 102 from the load 123. For example, since a gain of the third FET 103 is about 4 dB, power is about 4 dB lower than that in the maximum output state. However, high-efficiency operation is possible because the third FET 103 is not in operation. Moreover, it is also possible to realize high-efficiency operation at an output, which is lower than that by 4 dB, by setting the switch 124 in the OFF state and the second FET 102 in an ON state. A fine increase in efficiency may be realized in the neighborhood of the maximum output, by combination with a system of derivation from the preceding stage in an ordinary system. When such a fine increase in efficiency may not be of concern, the switch 125 or the switch 124 may be removed.

[3. Third Embodiment]

[0036] FIG. 6 is a diagram illustrating a configuration example of an amplifier according to the third embodiment.

[0037] An amplifier 100B according to the third embodiment is different from the amplifier 100 A according to the second embodiment, as follows. In this amplifier 100B, a switch 124A is connected to the drain of the first FET 101 and the drain of the third FET 103, and a switch 125 A is connected to the drain of the second FET 102 and the drain of the third FET 103.

[0038] The same effects as those of the amplifier 100 A according to the second embodiment may be obtained, when the switches are arranged as illustrated in FIG. 6. When finer efficiency control is desired, a power source is not limited to a battery, and a power circuit such as a DC-DC converter may be used.

[0039] Further, in general, stability may be weakened by bandwidth enhancement of a circuit. In this regard, stabilization is enabled by adding a stabilizing circuit to a basic circuit. A configuration in which the stabilizing circuit is added to a basic circuit will be described as a fourth embodiment. [4. Fourth Embodiment]

[0040] FIG. 7 is a diagram illustrating a configuration example of an amplifier according to the fourth embodiment.

[0041] An amplifier lOOC according to the fourth embodiment is different from the amplifier 100 according to the first embodiment, as follows. Stabilizing circuits 131, 132, and 133 are arranged between the gate and the source, between the gate and the drain, and between the source and the drain of the first FET 101, respectively. Stabilizing circuits 134, 135, and 136 are arranged between the gate and the source, between the gate and the drain, and between the source and the drain of the second FET 102, respectively. Stabilizing circuits 137, 138, and 139 are arranged between the gate and the source, between the gate and the drain, and between the source and the drain of the third FET 103, respectively. The stabilizing circuits 131 to 139 are each formed of a resistance, an inductor, a capacitor, and the like.

[0042] In this way, weakening of stability due to the bandwidth enhancement of the circuit may be prevented by arranging the stabilizing circuits, and stabilization of the amplifier is enabled.

[0043] It is to be noted that, although the nine stabilizing circuits 131 to 139 are illustrated in FIG. 7, any number of stabilizing circuits may be incorporated as appropriate. The stabilizing circuit may be arranged between the gate and the source, between the gate and the drain, or between the drain and the source, of the first FET 101, as appropriate. Further, the stabilizing circuit may be arranged between the gate and the source, between the gate and the drain, or between the drain and the source, of the second FET 102, as appropriate. Furthermore, the stabilizing circuit may be arranged between the gate and the source, between the gate and the drain, or between the drain and the source, of the third FET 103, as appropriate.

[5. Fifth Embodiment]

[0044] FIG. 8 is a diagram illustrating a configuration example of an amplifier according to the fifth embodiment.

[0045] An amplifier 100D according to the fifth embodiment is different from the amplifier 100 according to the first embodiment, as follows. This amplifier 100D is configured such that, gate biases of the first FET 101, the second FET 102, and the third FET 103 are applied from a single supply point, instead of being applied individually.

[0046] The gate biases of the respective FETs may or may not be separately applied. When a variation in the FETs is little, the gate biases may be applied from the single supply point as illustrated in the figure. Also, a configuration may be employed in which two FETs are applied with gate biases based on a certain voltage while one FET is applied with a gate bias based on another voltage, and any combination of such factors may be employed.

[6. Sixth Embodiment]

[0047] FIG. 9 is a diagram illustrating a configuration example of an amplifier according to the sixth embodiment.

[0048] An amplifier 100E according to the sixth embodiment is different from the amplifier 100 according to the first embodiment, as follows. In this amplifier 100E, passive devices or passive circuits 141 to 143 such as stripe lines are arranged, in place of the capacitors 116 to 118 serving as isolation devices.

[0049] In the amplifier 100 of FIG. 1 , the connection between the gates has been described as being provided through the capacitor. However, an optional passive device or passive circuit may be used instead of the capacitor, as illustrated in FIG. 9.

[7. Seventh Embodiment]

[0050] FIG. 10 is a diagram illustrating a configuration example of an amplifier according to the seventh embodiment.

[0051] An amplifier 100F according to the seventh embodiment is different from the amplifier 100 according to the first embodiment, as follows. This amplifier 100F has a configuration in which FETs are in more than three stages instead of three stages (three-stage serial connection).

[0052] In all of the first to sixth embodiments, although the FETs in three stages have been described, a configuration of two stages, or four or more stages as illustrated in FIG. 10, may also be acceptable. In addition, the active device to be used is not limited to the FET, and may be other devices such as a HBT and a CMOS.

[8. Eighth Embodiment]

[0053] FIG. 11 is a diagram illustrating a configuration example of an amplifier according to the eighth embodiment.

[0054] An amplifier 100G according to the eighth embodiment is different from the amplifier 100 according to the first embodiment, as follows. In this amplifier lOOG, a preamplifier 150 and a matching circuit 151 are cascade-connected between the input terminal 106 and the input node NDI. Further, a switch 152 such as an FET switch and a matching circuit 153 are cascade-connected between a connection node ND and an input section of the matching circuit 107. The connection node ND is provided between an output of the preamplifier 150 and an input of the matching circuit 151. The input section of the matching circuit 107 is provided on an output side of the amplifier 100G.

[0055] The preamplifier (an amplifier) 150 may be provided in a preceding stage when a gain is insufficient in a configuration such as that in each of the first to seventh embodiments. In the case of providing the amplifier in the preceding stage, the switch 152 may be provided at the output thereof and connected to the output, so that high efficiency with a lower output is possible. Further, switching of the matching circuit may be performed when a band of the preceding stage is not enough.

[0056] The whole or a part of each of the circuits described above may be configured on a MMIC (Monolithic Microwave Integrated Circuit). A part that is not mounted on the MMIC may be arranged on a module substrate or a set substrate such as an organic substrate.

[9. Ninth Embodiment]

[0057] FIG. 12 is a circuit diagram illustrating a configuration example of an amplifier according to the ninth embodiment.

[0058] An amplifier 100H according to the ninth embodiment is different from the amplifier 100G according to the eighth embodiment, as follows. This amplifier 100H is configured such that a band changeover switch 154 is provided on an output side of a matching circuit 107 to obtain a plurality of RF outputs. Further, in the amplifier 100H, matching circuits 158, 159, and 160 are arranged between each output of the band changeover switch 154 and RF output terminals 155, 156, and 157, respectively.

[0059] In this way, the switch 154 for band change may be arranged at the output of the amplifier 100H, as illustrated in FIG. 12. In this case, the output matching circuits 158 to 160 may be further provided after the band change, to achieve higher performance.

[10. Tenth Embodiment]

[0060] FIG. 13 is a diagram illustrating a configuration example of a wireless communication unit according to the tenth embodiment.

[0061] In this wireless communication unit 200, a transceiver 201 is arranged in an input stage of an amplifier 1001. In the wireless communication unit 200, a duplexer 161 is provided as a filter on an output side of a band changeover switch 154, and an antenna switch 162 that selectively connects an antenna ATN is provided on an output side of the duplexer 161.

[0062] In addition, in the amplifier 1001 applied to the wireless communication unit 200, further, a preamplifier 163 and a matching circuit 164 may be cascade-connected between an output of the transceiver 201 and an input of a preamplifier 150. Moreover, a switch 165 such as an FET switch and a matching circuit 166 may be cascade-connected between a connection node ND2 and an input section of the matching circuit 107. The connection node ND2 may be provided between an output of the preamplifier 163 and an input of the matching circuit 164. The input section of the matching circuit 107 may be provided on an output side of the amplifier 1001.

[0063] Any of the amplifiers 100 to 100H according to the first to ninth embodiments is applicable to the wireless communication unit 200 of the tenth embodiment, and effects similar to those in each of the above-described amplifiers may be attainable. In other words, in the amplifier 100 of one embodiment of the technology, signals may be input together from the input to the gates of the first FET 101, the second FET 102, and the third FET 103. For this reason, the first FET 101, the second FET 102, and the third FET 103 each act as an amplifier, and thus are allowed to provide a high gain as an amplifier. In other words, according to the amplifiers of the example embodiments, bandwidth enhancement that supports multiple bands, which is unsupportable by ordinary techniques, is achievable, and a high-efficiency small PA (a power amplifier) is maybe realized. Further, a PA capable of achieving high efficiency is realized in a maximum output state and in an output-reduced state. Therefore, according to the wireless communication unit 200, radio transmission is may be performed stably.

[11. Eleventh Embodiment]

[0064] Now, a description is given on an amplifier 300 according to an eleventh embodiment, in which the amplifier 300 is structured by two FETs and a gate of the FET of second stage is grounded through a capacitor. Note that the same or equivalent elements as those of the amplifier 100 according to the first embodiment described above are denoted with the same reference numerals, and will not be described in detail.

[0065] FIG. 14 illustrates a configuration example of the amplifier 300 according to the eleventh embodiment. The amplifier 300 includes the first FET 101, the second FET 102, a bias circuit 319, a stabilizing circuit 310, and a capacitor 317.

[0066] The drain of the second FET 102 is led to the power source 114 through the bias supply circuit 110, and is also led to the load 123 through the matching circuit 107. In other words, while the amplifier 100 is structured using three FETs in the first embodiment as illustrated in FIG. 1, the amplifier 300 is structured using two FETs in the eleventh embodiment. The bias supply circuits 108 to 110 may be integrated on the same chip as elements such as the two FETs, or may be configured as components provided separately from the chip on which elements such as the two FETs are integrated. The bias circuit 319 applies a bias voltage to the gate of the first FET 101 through the resistive device 120, and applies the bias voltage to the gate of the second FET 102 through the resistive device 121. The stabilizing circuit 310 serves to increase stability of the amplifier 300, and is provided between the gate of the first FET 101 and the gate of the second FET 102. In this embodiment, the gate of the first FET 101 is connected directly to the input terminal 106.

[0067] The capacitor 317 serves to allow an impedance between the gate of the second FET 102 and the ground to have a predetermined value. A first end of the capacitor 317 is connected to the gate of the second FET 102, and a second end thereof is grounded. In other words, for example, while the gate of the second FET 102 is led to the input terminal 106 through the input node NDI and the capacitor 117 in the first embodiment as illustrated in FIG. 1, the gate of the second FET 102 is grounded through the capacitor 317 in the present embodiment.

[0068] The capacitor 317 has a capacitance value so set as to allow an impedance, at a frequency of an input signal fed to the amplifier 300, to have a predetermined value. In the amplifier 300, the impedance of the capacitor 317 is set to a predetermined value, thereby making it possible to achieve a high gain and a high efficiency as well as to increase linearity of transfer characteristics. In the following, the impedance of the capacitor 317 is described in detail.

[0069] FIG. 15 illustrates a circuit configuration or a fundamental circuit of a major part of the amplifier 300. In FIG. 15, the capacitor 317 is illustrated as a device 301 that has a predetermined impedance Z, and illustration of the stabilizing circuit 310 is omitted in FIG. 15 for simplicity. An output terminal 306 is connected to the drain of the second FET 102, and is led to the load 123 through the matching circuit 107 as illustrated in FIG. 14. A voltage Vgl is a gate voltage of the first FET 101, and a voltage Vdl is a drain voltage of the first FET 101. A voltage Vs2 is a source voltage of the second FET 102, and a voltage Vg2 is a gate voltage of the second FET 102. A voltage Vd2 is a drain voltage of the second FET 102.

[0070] FIG. 16 illustrates a high-frequency equivalent circuit of the fundamental circuit illustrated in FIG. 15. Cgsl denotes a gate capacitance of the first FET 101. Idsl denotes a drain current of the first FET 101, and is expressed by (gml ^χ Vgsl) as the product of a transconductance gml of the first FET 101 and a gate-source voltage Vgsl of the first FET 101. Also, Cgs2 denotes a gate capacitance of the second FET 102. Ids2 denotes a drain current of the second FET 102, and is expressed by (gm2 ^χ Vgs2) as the product of a transconductance gm2 of the second FET 102 and a gate-source voltage Vgs2 of the second FET 102. It is to be noted that illustration of the resistive device 121 is omitted in FIG. 16, since an impedance of the resistive device 121 is sufficiently greater than the impedance of the device 301.

[0071] FIG. 17 schematically illustrates an amplifying operation of the fundamental circuit. A signal fed to the input terminal 106 is fed first to the gate of the first FET 101. Here, the signal is applied as the gate-source voltage Vgsl in the first FET 101 , since the source of the first FET 101 is grounded. The signal fed to the source of the first FET 101 is amplified and inverted by the first FET 101, following which the resultant signal is output from the drain of the first FET 101. The thus-output signal is fed as the source voltage Vs2 to the source of the second FET 102 through the capacitor 104. Here, a waveform in phase with a waveform of the source voltage Vs2 of the second FET 102 appears in the gate (the gate voltage Vg2) of the second FET 102. The signal fed to the source of the second FET 102 is amplified by the second FET 102, and the resultant signal is output as the voltage Vd2.

[0072] The amplifying operation of the fundamental circuit described above is discussed in greater detail below. In the following description, an example is given where the first FET 101 and the second FET 102 are of devices having the same layout dimension (for example, same in gate width and gate length). In other words, in this example, the first FET 101 has current characteristics same as those of the second FET 102.

[0073] First, the source voltage Vs2 of the second FET 102 is expressed by Expression (1) as follows using the gate-source voltage Vgsl of the first FET 101, where Avl is a voltage gain derived from the first FET 101.

Vs2 = -Avl x Vgsl (1)

[0074] Also, the gate voltage Vg2 of the second FET 102 is expressed by Expression (2) as follows using the above source voltage Vs2, where Zcgs2 is an impedance of a gate capacitance Cgs2.

Vg2 = Vs2 Z / (Z + Zcgs2) (2)

[0075] The gate-source voltage Vgs2 of the second FET 102 is expressed by Expression (3) as follows using the above Expressions (1) and (2).

Vgs2 = Vg2 - Vs2

= Vgsl x Avl x Zcgs2 / (Z + Zcgs2) (3) [0076] In the fundamental circuit, the first FET 101 and the second FET 102 are connected in series. Hence, the drain current Idsl defined by (gml ^χ Vgsl) of the first FET 101 and the drain current Ids2 defined by (gm2 ^χ Vgs2) of the second FET 102 are substantially equal to each other. Also, the dimension of the first FET 101 and the dimension of the second FET 102 are equal to each other. Hence, the transconductance gml of the first FET 101 and the transconductance gm2 of the second FET 102 are substantially equal to each other. Therefore, it is preferable that the gate-source voltage Vgsl of the first FET 101 and the gate-source voltage Vgs2 of the second FET 102 be substantially equal to each other, as expressed by Expression (4) as follows.

Vgsl = Vgs2 (4)

[0077] Expression: Avl ^χ Zcgs2 / (Z + Zcgs2) = 1 is satisfied using the above Expressions (3) and (4). Upon simplifying this Expression with respect to the impedance Z, the following Expression (5) is satisfied.

Z = (Avl - 1) x Zcgs2

= (Avl - l) / (j 2π f Cgs2) (5)

[0078] As expressed by the Expression (5), the impedance Z of the device 317 connected to the gate of the second FET 102 is determined by the voltage gain Avl of the first FET 101 and the impedance Zcgs2 of the gate capacitance in the second FET 102. The impedance Zcgs2 is determined by a frequency "f of an input signal and the gate capacitance Cgs2 of the second FET 102. For example, imaginary part of the impedance Z is of about tens of ohm (Ω). Incidentally, a circuit is proposed in a related art (Japanese Unexamined Patent Application Publication No. 2008-236354) in which, for example, a gate of an FET of second stage is provided with a quarter wavelength transmission line. It is to be noted, however, that the FET of second stage, etc., is introduced therein for the purpose of impedance conversion, and the quarter wavelength transmission line is provided for the purpose of supplying the gate with a bias as well as of allowing an impedance to be infinity at a frequency of an input signal. Hence, embodiments according to the present technology differ from the related art discussed above.

[0079] According to the amplifier 300 of the present embodiment, the gate of the second FET 102 is grounded through the device 301 having the predetermined impedance Z as described above, making it possible to allow the gate-source voltage Vgsl of the first FET 101 and the gate-source voltage Vgs2 of the second FET 102 to be substantially equal to each other. As is apparent from the Expression (5), the impedance Z is the same as the impedance in the capacitor whose capacitance value is defined as Cgs2 / (Avl - 1). Hence, the capacitor 317 may be used as the device 301 as illustrated in FIG. 14. The capacitor 317 has a predetermined impedance as described above, which is therefore different from a so-called bypass capacitor that serves to sufficiently reduce an impedance for AC-wise grounding.

[0080] In the present embodiment, the capacitor 317 is used as the device 301 , although it is not limited thereto. Any device may be used for the device 301 as long as a configuration is established that achieves the predetermined impedance Z at a frequency of an input signal.

[0081] According to the eleventh embodiment of the technology, the gate of the second FET is grounded through the device having the predetermined impedance at the frequency of the input signal. Hence, it is possible to achieve a high gain and a high efficiency as well as to increase linearity of transfer characteristics.

[Modification 11-1]

[0082] In the eleventh embodiment described above, the capacitor 317 is used as the device 301 having the predetermined impedance Z, although this is not limitative. For example, in one embodiment, a variable capacitor 317B may be used as illustrated in FIG. 18. The variable capacitor 317B achieves a configuration in which a plurality of capacitors provided therein are switched over from one to another by a switch, for example. This makes it possible to, for example, vary the impedance Z in response to the frequency of the input signal. Hence, according to the modification 11-1, it is possible to amplify signals at various frequencies with use of the single amplifier, and to optimize a power efficiency for each frequency.

[Modification 11-2]

[0083] In the eleventh embodiment described above, the stabilizing circuit 310 is provided, although this is not limitative. For example, in one embodiment, the stabilizing circuit 310 may be eliminated as illustrated in FIG. 19.

[Modification 11-3]

[0084] In the eleventh embodiment described above, the amplifier 300 is structured using two FETs, although this is not limitative. For example, in one embodiment, three or more FETs may be used to configure the amplifier. In the following, some embodiments where the amplifier is structured by three FETs are described in detail with reference to several examples.

[0085] FIG. 20 illustrates a configuration example of an amplifier 300D according to a modification 11-3. The amplifier 300D includes the third FET 103, a stabilizing circuit 311, and a capacitor 318.

[0086] The source of the third FET 103 is led to the drain of the second FET 102 through the capacitor 105. The drain of the third FET 103 is led to the power source 115 through the bias supply circuit 112, and is also led to the load 123 through the matching circuit 107. In other words, three FETs are used to structure the amplifier 300D in the present modification. The stabilizing circuit 311 serves to increase stability of the amplifier 300D, and is provided between the gate of the first FET 101 and the gate of the third FET 103. A first end of the capacitor 318 is connected to the gate of the third FET 103, and a second end thereof is grounded.

[0087] The capacitor 318 has a capacitance value so set as to allow an impedance, at a frequency of an input signal, to have a predetermined value. More specifically, it is preferable that the impedance Z of the capacitor 318 be set based on Expression (6) as follows, as with the eleventh embodiment described above.

Z = (Avl2 - 1) Zcgs3

= (Avl2 - 1)/G ^χ 2π f ^χ Cgs3) (6)

[0088] In the Expression (6), Cgs3 denotes a gate capacitance of the third FET 103, and Zcgs3 denotes an impedance of the gate capacitance Cgs3. Avl2 denotes a voltage gain derived from two stages of amplifiers structured by the first FET 101 and the second FET 102. Here, the voltage gain Avl2 is greater than the voltage gain Avl. Hence, the impedance Z of the capacitor 318 is greater than the impedance Z of the capacitor 317 when the first FET 101, the second FET 102, and the third FET 103 are the same in dimension with respect to one another. In other words, the capacitance value of the capacitor 318 is smaller than the capacitance value of the capacitor 317.

[0089] In this example, the capacitor 318 is connected to the gate of the third FET 103, although this is not limitative. Any device may be used instead of the capacitor 318 as long as a configuration is established that achieves the predetermined impedance Z.

[0090] Also, in the amplifier 300D, the gate of the second FET 102 is grounded through the capacitor 317, and the gate of the third FET 103 is grounded through the capacitor 318, although this not limitative.

[0091] For example, the gate of the second FET 102 may be led to the input node NDI through the capacitor 317, and the gate of the third FET 103 may be grounded through the capacitor 318, as illustrated in FIG. 21. In this example, the input node NDI and the gate of the first FET 101 may be connected to each other through the capacitor 116 as illustrated in FIG. 22, for example.

[0092] Also, for example, the gate of the second FET 102 may be grounded through the capacitor 317, and the gate of the third FET 103 may be led to the input node NDI through the capacitor 318, as illustrated in FIG. 23. In this example, the input node NDI and the gate of the first FET 101 may be connected to each other through the capacitor 116 as illustrated in FIG. 24, for example.

[0093] In such examples described above as well, the capacitance values of the respective capacitors 317 and 318 may be set with reference to the Expressions (5) and (6). The Expressions (5) and (6) may be used when an impedance of the input node NDI is sufficiently low.

[Modification 11-4] [0094] Any combination of features from the second embodiment to the tenth embodiment described above may be applied to the amplifier 300 according to the eleventh embodiment or to any of the modifications thereof. Such combinations are also considered as preferred ones of embodiments according to the technology.

[12. Twelfth Embodiment]

[0095] Now, a description is given on an amplifier 400 according to a twelfth embodiment, in which the amplifier 400 is structured by two FETs and a gate of the FET of second stage is led to the input node NDI through a capacitor. Note that the same or equivalent elements as those of the amplifier 300 according to the eleventh embodiment described above are denoted with the same reference numerals, and will not be described in detail.

[0096] FIG. 26 illustrates a configuration example of the amplifier 400 according to the twelfth embodiment. The first end of the capacitor 317 is connected to the gate of the second FET 102, and the second end thereof is connected to the input node NDI. In other words, for example, while the gate of the second FET 102 is led to the ground through the capacitor 117 in the eleventh embodiment as illustrated in FIG. 14, the gate of the second FET 102 is led to the input node NDI through the capacitor 317 in the present embodiment.

[0097] The capacitor 317 has a capacitance value so set as to allow an impedance to have a predetermined value at a frequency of an input signal, as in the eleventh embodiment described above (with use of the Expression (5), etc.). Hence, as with the amplifier 300 described above, the amplifier 400 makes it possible to achieve a high gain and a high efficiency as well as to increase linearity of transfer characteristics. In particular, the gate of the second FET 102 is led to the input node NDI through the capacitor 317, thus forming a negative feedback circuit in the amplifier 400. This makes it possible to further stabilize an operation in the amplifier 400.

[0098] According to the twelfth embodiment, the gate of the second FET is led to the input node through the device having the predetermined impedance at a frequency of an input signal. Hence, in addition to similar advantageous effects achieved by the eleventh embodiment described above, the twelfth embodiment makes it possible to achieve further stabilization of an operation in the amplifier.

[Modification 12-1]

[0099] In the twelfth embodiment described above, the capacitor 317 is used as the device 301 having the predetermined impedance Z, although this is not limitative. For example, in one embodiment, the variable capacitor may be used as in the modification 11-1 described above.

[Modification 12-2]

[0100] In the twelfth embodiment described above, the input node NDI and the gate of the first FET 101 are connected to each other directly, although this is not limitative. For example, in one embodiment, the input node NDI and the gate of the first FET 101 may be connected through the capacitor 116 as illustrated in FIG. 26.

[Modification 12-3]

[0101] In the twelfth embodiment described above, the amplifier 400 is structured using two FETs, although this is not limitative. For example, in one embodiment, three or more FETs may be used to configure the amplifier as illustrated in FIG. 27. In this example, the gate of the third FET 103 is led to the input node NDI through the capacitor 318. Also, the input node NDI and the gate of the first FET 101 may be connected through the capacitor 116 as illustrated in FIG. 28, for example. In such examples as well, the capacitance values of the respective capacitors 317 and 318 may be set with reference to the Expressions (5) and (6).

[Modification 12-4]

[0102] Any combination of features from the second embodiment to the tenth embodiment described above may be applied to the amplifier 400 according to the twelfth embodiment or to any of the modifications thereof. Such combinations are also considered as preferred ones of embodiments according to the technology.

[0103] Accordingly, it is possible to achieve at least the following configurations from the above-described example embodiments and the modifications of the disclosure:

(1) An amplifier, including:

a plurality of stages of field-effect transistors including a first field-effect transistor and a second field-effect transistor provided in series between a ground and an output load; and

a first capacitor provided between a drain of the first field-effect transistor and a source of the second field-effect transistor,

wherein the source of the first field-effect transistor is grounded,

the drain of the field-effect transistor of final stage is led to the output load through a first matching circuit, and

gates of the plurality of stages of field-effect transistors are led to a signal input node. (2) The amplifier according to (1), wherein

the drain of each of the plurality of stages of field-effect transistors is led to a power source through a bias device,

the source of the FET other than the first field-effect transistor is led to the ground through a bias device, and

the gate of each of the plurality of stages of field-effect transistors is led to a bias circuit biasing a gate potential.

(3) The amplifier according to (1) or (2), wherein the drain of the first field-effect transistor is allowed to be connected to the drain of the second field-effect transistor through a switch.

(4) The amplifier according to (1) or (2), further including a third field-effect transistor with a source and a drain as the field-effect transistor of final stage, the source being led to the drain of the second field-effect transistor through a second capacitor, and the drain being led to the output load through the first matching circuit.

(5) The amplifier according to (4), wherein the drain of the second field-effect transistor is allowed to be connected to the drain of the third field-effect transistor through a switch.

(6) The amplifier according to (4), wherein

the drain of the first field-effect transistor is allowed to be connected to the drain of the second field-effect transistor through a switch, and

the drain of the second field-effect transistor is allowed to be connected to the drain of the third field-effect transistor through a switch.

(7) The amplifier according to (4), wherein the drain of the first field-effect transistor is allowed to be connected to the drain of the third field-effect transistor through a switch.

(8) The amplifier according to (4), wherein

the drain of the first field-effect transistor is allowed to be connected to the drain of the third field-effect transistor through a switch, and

the drain of the second field-effect transistor is allowed to be connected to the drain of the third field-effect transistor through a switch.

(9) The amplifier according to any one of (1) to (8), wherein at least any one of the plurality of stages of field-effect transistors has a stabilizing circuit arranged at least any one of between the gate and the source, between the gate and the drain, and between the drain and the source, the stabilizing circuit allowing the corresponding field-effect transistor to be stabilized.

(10) The amplifier according to any one of (1) to (9), further including at least one preamplifier provided in a preceding stage of the signal input node.

(11) The amplifier according to (10), further including a switch provided between an output terminal of the preamplifier and the first matching circuit, the switch selectively supplying an output of the preamplifier to the first matching circuit.

(12) The amplifier according to any one of (1) to (11), further including a band changeover switch provided on an output side of the first matching circuit.

(13) The amplifier according to (12), further including a second matching circuit arranged at an output side of the band changeover switch.

(14) The amplifier according to (12), further including a filter arranged at an output side of the band changeover switch. (15) The amplifier according to (13) or (14), further including an antenna switch arranged on an output side of the second matching circuit or the filter arranged on an output side of the band changeover switch, the switch allowing a connection to an antenna.

(16) An amplifier, including:

a first field-effect transistor including a gate, a source, and a drain, the gate being led to a signal input node, and the source being grounded;

a first capacitor;

a first device having a predetermined first impedance value at a frequency of a signal fed to the signal input node; and

a second field-effect transistor including a gate, a source, and a drain, the gate being connected to the first device, and the source being led to the drain of the first field-effect transistor through the first capacitor.

(17) The amplifier according to (16), wherein the gate of the second field-effect transistor is grounded through the first device.

(18) The amplifier according to (16), wherein the gate of the second field-effect transistor is led to the signal input node through the first device.

(19) The amplifier according to any one of (16) to (18), wherein the first device includes a capacitor.

(20) The amplifier according to any one of (16) to (19), wherein the first device includes a variable capacitor.

(21) The amplifier according to any one of (16) to (20), further including a stabilizing circuit provided between the gate of the first field-effect transistor and the gate of the second field-effect transistor.

(22) The amplifier according to any one of (16) to (21), further including:

a second capacitor;

a second device having a predetermined second impedance value at the frequency of the signal fed to the signal input node; and

a third field-effect transistor including a gate, a source, and a drain, the gate being connected to the second device, and the source being led to the drain of the second field-effect transistor through the second capacitor.

(23) The amplifier according to (22), wherein the gate of the third field-effect transistor is grounded through the second device.

(24) The amplifier according to (22), wherein the gate of the third field-effect transistor is led to the signal input node through the second device.

(25) The amplifier according to any one of (22) to (24), wherein the second impedance value is greater than the first impedance value.

(26) The amplifier according to any one of (16) to (25), further including a third capacitor, wherein the signal input node is led to the gate of the first field-effect transistor through the third capacitor.

(27) A wireless communication unit with an amplifier that amplifies a signal to be transmitted and outputs the amplified signal, the amplifier including:

a plurality of stages of field-effect transistors including a first field-effect transistor and a second field-effect transistor provided in series between a ground and an output load; and

a first capacitor provided between a drain of the first field-effect transistor and a source of the second field-effect transistor,

wherein the source of the first field-effect transistor is grounded,

the drain of the field-effect transistor of final stage is led to the output load through a first matching circuit, and

gates of the plurality of stages of field-effect transistors are led to a signal input node.

(28) The wireless communication unit according to (27), wherein

the drain of each of the plurality of stages of field-effect transistors is led to a power source through a bias device,

the source of the FET other than the first field-effect transistor is led to the ground through a bias device, and

the gate of each of the plurality of stages of field-effect transistors is connected to a bias circuit biasing a gate potential.

(29) A wireless communication unit with an amplifier that amplifies a signal, the amplifier including:

a first field-effect transistor including a gate, a source, and a drain, the gate being led to a signal input node, and the source being grounded;

a first capacitor;

a first device having a predetermined first impedance value at a frequency of a signal fed to the signal input node; and

a second field-effect transistor including a gate, a source, and a drain, the gate being connected to the first device, and the source being led to the drain of the first field-effect transistor through the first capacitor. (30) An amplifier, comprising:

a set of field-effect transistors provided in series between a ground and an output load including:

a first field-effect transistor with a source connected to the ground, a second field-effect transistor, and a first capacitor connected between a drain of the first field-effect transistor and a source the second first field-effect transistor; and

a first device having a predetermined impedance value connected to a gate of the second field-effect transistor.

(31) The amplifier according to claim (30), wherein the first device is a capacitor.

(32) The amplifier according to any one of (30) to (31), wherein the predetermined impedance value is responsive to a frequency of an input signal.

(33) The amplifier according to any one of (30) to (32), wherein the predetermined impedance value is determined by a voltage gain of the first field-effect transistor and an impedance of a gate capacitance in the second field-effect transistor.

(34) The amplifier according to any one of (30) to (33), wherein the first device is a variable capacitor and the predetermined impedance value is a variable impedance value that is responsive to the frequency of an input signal.

(35) The amplifier according to any one of (30) to (34), wherein the variable capacitor includes a switch and a plurality of capacitors.

(36) The amplifier according to any one of (30) to (35), further comprising:

a bias circuit separately connected to the gates of the first and second field-effect transistors via a first resistive element and a second resistive element, respectively. (37) The amplifier according to any one of (30) to (36), further comprising:

a first stabilizing circuit connected between a gate of the first field-effect transistor and the gate of the second field-effect transistor.

(38) The amplifier according to any one of (30) to (37), further comprising:

a third field-effect transistor included in the set of field-effect transistors;

a second capacitor connected between a drain of the second field-effect transistor and a source the third first field-effect transistor; and

a second device having a second predetermined impedance value connected to a gate of the third field-effect transistor.

(39) The amplifier according to any one of (30) to (38), wherein the second predetermined impedance value is greater than the predetermined impedance of the first device when the first field-effect transistor, the second field-effect transistor, and the field-effect transistor are in the same dimension.

(40) The amplifier according to any one of (30) to (39), wherein the first device is connected to an input node.

(41) The amplifier according to any one of (30) to (40), wherein the first device and the second device are connected to an input node.

(42) The amplifier according to any one of (30) to (41), wherein the second device is connected to an input node.

(43) The amplifier according to any one of (30) to (42), further comprising:

a second stabilizing circuit connected between a gate of the first field-effect transistor and the gate of the third field-effect transistor. (44) The amplifier according to any one of (30) to (43), further comprising:

a second stabilizing circuit connected between a gate of the first field-effect transistor and the gate of the third field-effect transistor.

(45) An amplifier, comprising:

a set of field-effect transistors provided in series between a ground and an output load including:

a first field-effect transistor with a source connected to the ground, a second field-effect transistor,

a first capacitor connected between a drain of the first field-effect transistor and a source the second first field-effect transistor,

a third field-effect transistor included in the set of field-effect transistors, and

a second capacitor connected between a drain of the second field-effect transistor and a source the third first field-effect transistor;

a first device having a predetermined impedance value connected to a gate of the second field-effect transistor; and

a second device having a second predetermined impedance value connected to a gate of the third field-effect transistor,

wherein the predetermined impedance value is responsive to a frequency of an input signal.

(46) A wireless communication unit, comprising:

an amplifier that includes:

a first field-effect transistor with a source connected to the ground, a second field-effect transistor, and a first capacitor connected between a drain of the first field-effect transistor and a source the second first field-effect transistor; and

a first device having a predetermined impedance value connected to a gate of the second field-effect transistor.

(47) The wireless communication unit according to claim (46), wherein the predetermined impedance value is determined by a voltage gain of the first field-effect transistor and an impedance of a gate capacitance in the second field-effect transistor.

(48) The wireless communication unit according to any one of (46) to (47), wherein the amplifier further comprises:

a third field-effect transistor included in the set of field-effect transistors;

a second capacitor connected between a drain of the second field-effect transistor and a source the third first field-effect transistor; and

a second device having a second predetermined impedance value connected to a gate of the third field-effect transistor.

(49) The wireless communication unit according to any one of (46) to (48), wherein the second predetermined impedance value is greater than the predetermined impedance of the first device when the first field-effect transistor, the second field-effect transistor, and the field-effect transistor are in the same dimension.

[0104] The present disclosure contains subject matter related to that disclosed in each of Japanese Priority Patent Application JP 2012-045200 filed in the Japan Patent Office on March 1, 2012 and Japanese Priority Patent Application JP 2012-258403 filed in the Japan Patent Office on November 27, 2012, the entire content of each of which is hereby incorporated by reference. [0105] Although the technology has been described in terms of exemplary embodiments, it is not limited thereto. It should be appreciated that variations may be made in the described embodiments by persons skilled in the art without departing from the scope of the technology as defined by the following claims. The limitations in the claims are to be interpreted broadly based on the language employed in the claims and not limited to examples described in this specification or during the prosecution of the application, and the examples are to be construed as non-exclusive. For example, in this disclosure, the term "preferably", "preferred" or the like is non-exclusive and means "preferably", but not limited to. The use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another. Moreover, no element or component in this disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.