The present invention relates to an amplifier device and to an amplifier. The amplifier and device find use in particular, although not limited to, audio amplification. The present invention also relates to a method of operating an amplifier, in particular a Class D amplifier.

The amplification of signals, for example audio signals, is well known in the art. The design and implementation of improved amplifier architectures to provide accurate and stable amplification of input signals has received much attention and is the subject of considerable ongoing development.

US 3,970,953 discloses a distortion-free amplifier for electric signals. The amplifier comprises a first amplifier section of high quality and low power. The amplifier further comprises a second, high power amplifier. In use, the output signals of the first and second amplifiers is combined and applied to the load. In use, the second amplifier delivers the major portion of the current to the load. The amplifier employs feedback to improve the quality and accuracy of the amplified signal. In particular, a feedback signal is derived from the output of the second amplifier. The feedback signal is applied to the inputs of both the first and second amplifiers negatively in an amount to remove distortion from the combined output signals of both the first and second amplifiers. The amplifier architecture disclosed in US 3,970,953 is often referred to as a current dumping amplifier. The object of the amplifier proposed in US 3,970,953 was to reduce the need for bias control in bipolar transistors comprised in the second amplifier. To this end, US 3,970,953 discloses the use of a combination of a Class A amplifier as the first, low power amplifier and a Class B amplifier as the second, high power amplifier. In particular, there is proposed a low power Class A amplifier, with a signal swing extending between the limits of the power rails, the output of which is connected both directly to the load, as noted above, and to the base drive

connections of the transistors forming the Class B amplifier. The output of the Class B amplifier is connected to the load, such that the output signals of both amplifiers is combined. In use, with a small input signal applied to the system, the Class A amplifier drives the load, with the Class B amplifier contributing no signal. As the input signal increases, the Class B amplifier is activated and provides the majority of the drive to the load. The transition between the operation of the Class A amplifier only and the operation of the hybrid Class A/Class B combination is controlled by the feedback signals and is required to correct the non-linear behaviour of the Class B amplifier.

While the configuration disclosed in US 3,970,953 is effective in reducing distortion arising due to amplification of the input signal, the arrangement cannot reduce distortion at all operating frequencies to the required degree.

A number of improvements to the general amplifier arrangement of US 3,970,853 have been proposed.

US 4,107,619 discloses a constant voltage - constant current high fidelity amplifier. The amplifier employs a circuit comprising a cascade of transistors to maintain a constant voltage. This circuit is used as a low power amplifier to provide a relatively distortion free, voltage stabilised signal to a second, high power amplifier of constant current output and a gain of less than unity. Feedback is applied to the first, low power amplifier, with the second amplifier being outside the feedback loop of the first amplifier. The currents output by the two amplifiers are combined, whereby the majority of the work to drive the load is provided by the second amplifier, while the sonic quality of the drive signal is derived from the first amplifier. It is suggested in US 4, 107,619 that, by maintaining nearly constant current through the load and constant voltage across the amplifier, distortion may be reduced by from 10 to 30 times.

US 4,185,249 discloses a bipolar signal to current converter or a so-called 'current pump'. The arrangement provides for an input having a voltage signal to be applied to an amplifier. The output of the amplifier is provided to an output via a resistance. The voltage across the resistance is coupled to a differential amplifier, producing a voltage at its output that is applied to the input of the amplifier, to reduce its current to zero. US 4,185,249 suggests that this arrangement allows for the input signal to be amplified independently of the amplifier gain and the impedance of the load.

GB 2,058,501 discloses an amplifier device, in particular for use in amplifying audio frequency signals. The amplifier device comprises a pre-amplifier, a first amplifier for amplifying the output of the pre-amplifier and applying it through a first impedance element to a load. A negative feedback circuit is provided for feeding back the outputs of the first amplifier to the input of the pre-amplifier. The device further comprises a second amplifier, to which the inputs of the first amplifier are applied. The output of the second amplifier is applied to the load via a second impedance element. In this way, it is suggested that the second amplifier will act to cancel the distortion arising in the first amplifier. A similar arrangement is disclosed in US 4,367,442. US 4,523, 152 discloses a high efficiency feedforward - error - correction amplifier, with a view to providing amplification at both high efficiency and low levels of distortion. In the amplifier, the output signals of linear and switching circuits are summed together, with both circuits supplying power in parallel to a load. In particular, the output current is predominantly provided by to the load by the switching circuits, with the linear circuit operating with low average output current. This parallel arrangement may be applied in series with an alternative arrangement, in which the linear and switching circuits are arranged in series, in which power is supplied in a series manner from the switching circuits to the linear circuit and then to the load.

US 4,716,378 concerns an amplifier circuit, in particular for use in audio appliances. The amplifier circuit comprises two amplifiers. A first amplifier is provided to control the output voltage of the circuit. A second amplifier is provided to drive the output current to the load. An impedance circuit is connected to the outputs of both the first and second amplifiers.

More recently, US 7,545,212 discloses a Class AD audio amplifier. The amplifier comprises a voltage generator and a current generator. The voltage generator is described as having a high linearity and a very low output impedance. The signal to be amplified is provided to the input of the voltage generator. The output of the voltage generator is applied to the output of the current generator at a coupling point. A control stage controls the current generator according to the current being output by the voltage generator at the coupling point.

As described above, the general configuration of the known amplifiers employs a first, generally low powered amplifier, the output from which is applied to the input of a second, high powered amplifier, to provide the current required to drive the load under normal operating conditions. As also described above, much attention has been paid to arranging the amplifier to reduce distortion generated in the second, high power amplifier. A significantly improved amplifier architecture has now been found that provides for an accurate amplification of an input signal across a very wide range of frequencies, with a very low level of distortion. In particular, it has been found that a Class D amplifier can be employed to significant effect as the second, high powered amplifier.

Accordingly, in a first aspect, the present invention provides an amplifier device comprising:

a signal input for a signal to be amplified;

an amplified signal output for connection to a load to be driven by the device; a first amplifier assembly being a low power voltage amplifier, having an input connected to the signal input and an output;

a second amplifier assembly comprising a Class D amplifier having an input connected to the output of the low power voltage amplifier and an output;

wherein the output of the first amplifier assembly and the output of the second amplifier assembly are both connected to the amplified signal output.

The amplifier device of the present invention comprises a first amplifier assembly. The first amplifier assembly is a low power, voltage amplifier which, in use, receives the input signal to be amplified. The amplifier assembly is

characterised by being able to accurately amplify the input signal and operable at the full range of frequencies to be amplified. The reference to the first amplifier assembly being 'low power' is a reference to the duty of the first amplifier assembly relative to that of the second amplifier assembly. In particular, the first amplifier assembly is operable to provide an amplified signal with a low current output. In use, at low input signal strengths, the output of the first amplifier assembly is providing a significant portion of the drive to the load at low current. In preferred embodiments, the second amplifier assembly is arranged such that it ceases to operate at input signals below a threshold strength, thereby leaving the first amplifier assembly to provide all the output signal to the load.

The first amplifier assembly may be any suitable amplifier or combination of amplifiers to function as a low power, voltage amplifier. The first amplifier assembly is preferably a linear analogue amplifier. For example, the first amplifier may be one or more Class A amplifiers. Suitable Class A amplifiers are well known in the art and are commercially available. Alternatively, the first amplifier assembly may be a Class AB amplifier. Again, Class AB amplifiers suitable for use as the first amplifier are both well known in the art and are commercially available. Other suitable

configurations of one or more amplifiers may be used for the first amplifier assembly in the device of the present invention.

In one embodiment, the first amplifier assembly comprises an amplifier arrangement of the general kind disclosed in US 3,970,953, that is a current dumping amplifier, as described hereinbefore.

As noted, the output of the first amplifier assembly is applied both to the input of the second amplifier assembly and to the signal output of the device, for applying to the load, such as an audio speaker. The output of the first amplifier assembly is preferably connected to the signal output through one more resistance or impedance loads. In this way, the output and operation of the first amplifier assembly may be balanced to that of the second amplifier assembly, in particular by appropriate selection of the values of the impedances at the outputs of the first and second amplifier assemblies, as described in more detail hereinafter.

In one preferred embodiment, the first amplifier assembly comprises a plurality of individual amplifiers. In particular, the first amplifier assembly may comprise first and second amplifiers, arranged such that the output of the first amplifier is applied to the input of the second amplifier, which is operable to further amplify the voltage signal output by the first amplifier. The output of the second amplifier may be applied to the signal output of the device for applying to the load, when in use, as described hereinbefore. The first and second amplifiers of the first amplifier assembly may each be any suitable amplifier, for example a Class A amplifier or a Class AB amplifier. In one preferred arrangement, the first amplifier assembly comprises a first amplifier, and a second amplifier that is a current dumping amplifier having the general configuration set out in US 3,970,953.

The first amplifier assembly may be provided with one or more feedback loops. In particular, the first amplifier assembly may be provided with a loop to apply a signal from its output back to its input through a suitable impedance or impedance network. Alternatively or in addition thereto, the first amplifier assembly may be provided with a loop to apply a signal from the combined output of the first and second amplifier assemblies, for example at the signal output of the device, to the input of the first amplifier assembly. In this way, the total error in the combined output signal of both the first and second amplifier assemblies is input to the first amplifier assembly. Still further, in embodiments of the invention in which the first amplifier assembly comprises a configuration of two or more amplifiers, the assembly may be provided with one or more internal feedback loops for the individual amplifiers therein.

The amplifier device of the present invention further comprises a second amplifier assembly. The second amplifier assembly comprises a Class D amplifier. The second amplifier assembly is a high power amplifier, capable of amplifying a current applied to its input. In normal use, the second amplifier assembly is operating, together with the first amplifier assembly, to provide a signal to the signal output of the device. The second amplifier assembly generally provides the major portion of the signal current to the signal output, when the second amplifier assembly is operating.

The second amplifier assembly may operate at all input signal conditions. More preferably, as noted above, the second amplifier assembly is arranged to operate at all input signal conditions, except low input signal strengths, when the first amplifier assembly provides all of the signal output by the device. In particular, the second amplifier assembly may be arranged to operate only above a predetermined threshold strength of input signal. An arrangement for providing the second amplifier assembly with a threshold signal voltage, below which the amplifier ceases to operate is described hereinafter.

Class D amplifiers suitable for use in the second amplifier assembly are known in the art. A Class D amplifier may be characterised as a switching amplifier, that is, all the power devices within the amplifier are operated as binary switches in either the fully on or fully off condition. The amplifier should have an architecture that reduces as much as possible the time taken for the power devices to transition between the fully on and fully off conditions. The power devices of the Class D amplifier are typically transistors, with metal-oxide-silicon field effect transistors (MOSFETs) being particularly preferred due to their low response time and efficiency of operation at high frequencies.

Class D amplifiers generally comprise the following components and have the general arrangement as follows. The amplifier comprises a signal generator which, in use, generates a triangular wave reference signal. The signal to be amplified is applied to the input of the amplifier and is compared with the triangular reference signal in a comparator. The output of the comparator is a pulse width modulated (PWM) signal. The PWM signal output by the comparator is applied to a switching controller and an output stage comprising the power devices, in particular MOSFETs, as noted above. The PWM signal is amplified in the power devices operated under the control of the switching controller and the amplified signal is output to a low-pass filter. The low-pass filter removes the switching components of the output signal and recovers the lower frequency signal of interest.

In the amplifier device of the present invention, the output of the low-pass filter is provided to the signal output of the device, either directly or through one or more resistances or impedances. The second amplifier assembly is preferably connected to the signal output of the device through an impedance, in particular a combination of inductive and capacitive impedances, as is known in the art for Class D amplifiers. As noted above, the first amplifier assembly is preferably connected to the signal output of the device through an impedance, in particular a resistive impedance. In this way, the operations of the first and second amplifier may be balanced by appropriate selection of the ratio of the output impedance of the first amplifier assembly to the output impedance of the second amplifier assembly.

Preferably, the first amplifier assembly is connected to the signal output of the device through one or more resistors having a combined impedance that is at least 100 times the impedance at the output of the second amplifier assembly, at the frequencies of interest, more preferably at least 200, still more preferably at least 500, still more preferably about 1000 times. The frequencies of interest are preferably audio frequencies.

The second amplifier assembly may comprise a single Class D amplifier of the general, known configuration as described above. Alternatively, the second amplifier assembly may comprise two more Class D amplifiers, in particular arranged in parallel.

In a particularly preferred arrangement, the second amplifier assembly comprises a single input stage, having a comparator and a switching controller, in combination with a plurality of Class D output stages arranged in parallel and operable at different phases. The switching controller is operable to selectively activate one or more of the output stages. The outputs of the plurality of parallel Class D output stages are combined, with the output signal of the second amplifier assembly being the sum of the plurality of parallel outputs. It has been found that this arrangement provides a much higher modulation frequency and allows for the use of a plurality of smaller, lower powered devices in the output stages. The smaller devices are faster to drive with an input signal and have a faster response time than a single higher powered Class D device. In use, one, some or all of the parallel Class D output stages may be operating, depending upon the input signal and the power requirements for amplification. In particular, under conditions of low to medium load, the controller preferably operates the plurality of output stages individually in succession for periods of time. In this way, the load of the second amplifier assembly may be shared across all of the plurality of output stages, reducing the duty of each individual device. This has been found to be a particularly effective manner of operating a plurality of smaller output devices. At conditions of higher load, the controller may operate two or more output stages concurrently, as dictated by the load placed on the second amplifier assembly.

As noted, the preferred arrangement is to provide a two or more Class D output stages in parallel, operating at different phases. Any suitable number of such output stages may be arranged in parallel, preferably at least three output stages, with four parallel output stages being a particularly effective arrangement. A higher number of output stages may be arranged in parallel if required, for example six or more output stages, in particular eight or more output stages, as determined by the power output requirements of the second amplifier assembly.

The second amplifier assembly is preferably provided with feedback, in particular with its output signal being applied to the input of the second amplifier assembly through a suitable impedance. A simple feedback loop applies the signal at the output of the low-pass filter through a suitable impedance to the input of the comparator. However, this form of feedback is generally crude and ineffective, leading to a poor amplified signal being generated in the amplifier. The feedback signal may be taken from the output of the low-pass filter an applied to the output side of the comparator of the Class D amplifier. In this case, as the output of the low- pass filter, is an analogue signal, the device comprises an analogue-to-digital converter, to generate an appropriate feedback signal from the output signal of the low pass filter, to correspond to the output of the comparator. While this form of feedback may be preferred, as providing a more accurate output signal and more effective amplification, the analogue-to-digital converter introduces an increased time delay in the signal processing of the amplifier assembly.

A particularly preferred embodiment employs a unique architecture for the Class D amplifier employing feedback from the output side of the low-pass filter. The unique architecture employs a modified arrangement of comparators for processing the input signal and dispenses with a generator to provide a triangular reference wave. In this particularly preferred embodiment, the signal output from the first amplifier assembly is input to the Class D amplifier of the second amplifier assembly and is applied, through a resistive network, to two reference voltage signals. At rest, these voltages are centred around reference voltage, preferably zero volts, and offset from each other by a small voltage. The voltage offset is preferably from 10 to 200 mV, more preferably from 20 to 150 mV, still more preferably from 40 to 120 mV. An offset of about 100 mV is particularly preferred. In use, the output signal from the first amplifier is applied to each of the two reference voltages, which retain their voltage offset with respect to each other. Each signal is applied to a respective comparator.

A feed back signal from the output side of the low-pass filter is applied through a resistive network to the input of each comparator. The feedback loop is characterised by the sum of the time delays through the Class D amplifier. The feedback signal is applied input of both comparators in analogous manner to the signal to be amplified to two reference voltage signals. This arrangement removes the need for an analogue-to-digital converter in the feedback, while at the same time providing for a particularly efficient feedback modified operation of the amplifier.

This arrangement offers a number of significant advantages. The feedback signal is sourced from the output side of the low-pass filter and fed directly to the input of each comparator. Accordingly, as there is no requirement for an Analogue- to-Digital converter, the speed of the device is increased and the cost of the device reduced.

Further, the aforementioned arrangement offers significant advantages in modulation of the signal. Typically, the power devices of a Class D amplifier are perpetually driving the signal applied to the low-pass filter from one rail to the opposing rail. In particular, conventional Class D amplifier architectures comprise output devices, in particular OSFETs, arranged in pairs across the rails. The amplifier operates with a PWM signal that reproduces the applied analogue signal using a combination of operation of both the power devices of the pair in the output stage. This requires the rapid switching of both of the devices in the pair on an off in a coordinated manner, with the input analogue signal being reproduced at any given time by a combination of the output of both output devices in the pair. As the input signal declines to zero, this is reproduced by the operation of both output devices for an equal amount of time. As the components behave in a non-ideal manner, this switching requirement gives rise to a loss of power. The aforementioned arrangement significantly reduces these losses. In particular, the analogue signal is reproduced by the switching on and off of just one of a pair of output devices. Thus, as the input signal swings through a positive voltage, a single output device, in particular a OSFET, is switched on and off, as required. As the signal declines to zero both output devices are switched off. As the signal swings through a negative voltage, the second of the output devices is operated in like manner to reproduce the analogue signal. This preferred architecture requires only the switching of a single output device of each pair at any stage in the signal. Further, at a signal of zero volts, all output devices are off, allowing the output signal from the amplifier device to be provided by the first amplifier assembly alone.

Still further, by employing a reference voltage with an offset for each of the first and second comparators, as described above, this allows the second amplifier assembly to be switched on and off at low loads. As noted above, the signal output from the first amplifier assembly is applied to the input of the second amplifier assembly. When the strength of this signal is below the value of the offset voltage applied to the reference voltage at the input of the second amplifier assembly, there is no load through the second amplifier assembly. As the strength of this signal increases above the offset voltage, load is applied to the second amplifier assembly and it operates. This is in contrast to conventional Class D amplifiers which generally operate even at very low loads. However, as noted above, at low loads, known Class D amplifiers become very non-linear in operation and produce a very poor amplified signal. The hereinbefore described architecture for the Class D amplifier has been found to be particularly advantageous in overcoming shortcomings in known Class D amplifier architectures. In particular, known Class D amplifiers are compromised in operation by variations in the rail voltages. To overcome these problems requires the use of sophisticated and expensive power supply devices. Further, known Class D amplifiers generally have an operating efficiency that varies according to the applied load. Still further, known architectures are limited in terms of the maximum modulation frequency that can be applied. Finally, when operating a low signal levels, the Class D amplifiers have excessive non-linearity. In a further aspect, the present invention provides an amplifier of the Class D, the amplifier comprising:

a first comparator having its input connected to a first reference voltage supply;

a second comparator having its input connected to a second reference voltage supply;

wherein the first reference voltage is offset from the second reference voltage;

an input for receiving a signal to be amplified and applying the signal to each of the first and second reference voltage supplies at the inputs of the first and second comparators;

a switching controller;

an output stage comprising:

a first output device;

a second output device;

the switching controller receiving outputs from the first and second

comparators and the first and second output devices operable in response to signals from the switching controller; and

a low-pass filter for receiving the combined output signals from the first and second output device, the filter having an output for a signal to be output by the amplifier.

The signal to be amplified is applied, through a resistive network, to two reference voltage signals. At rest, these voltages are centred around zero volts and are offset from each other by a small voltage. The voltage offset is preferably from 10 to 200 mV, more preferably from 20 to 150 mV, still more preferably from 40 to 120 mV. An offset of about 100 mV is particularly preferred. In use, the signal to be amplified is applied to each of the two reference voltages, which retain their voltage offset with respect to each other. Each signal is applied to a respective comparator.

The Class D amplifier may comprise a single switching controller and a single output stage, as is known in conventional architectures. In one preferred

arrangement, the amplifier comprises a plurality of output stages, with the output from the comparators being applied to the input of a switching controller operable to select the operation of one or more of the plurality of output stages, as described above. The configuration of the or each output stage is known in the art.

In a further aspect, the present invention provides a method of operating a Class D amplifier, in particular of modulating a signal for input to a Class D amplifier, the method comprising:

providing a first reference voltage supply;

providing a second reference voltage supply, having a voltage different from the first reference voltage supply;

applying the first reference voltage supply to the input of a first comparator; applying the second reference voltage supply to the input of a second comparator;

applying a signal for modulation to both the inputs of the first and second comparators;

whereby both of the first and second comparators generates a drive signal for an output stage of the amplifier.

As discussed hereinbefore, the input signal applied to each comparator is preferably combined with a feedback signal from the output of the amplifier, with the feedback signal preferably being taken from the output side of the low-pass filter of the amplifier and applied through a suitable resistive network to the input of each comparator.

Embodiments of the present invention will now be described, by way of example only, having reference to the accompanying drawings, in which:

Figure 1 is a general schematic diagram of an amplifier device of one embodiment of the present invention; Figure 2 is a schematic diagram of one Class D amplifier architecture for use in the amplifier device of Figure 1 ;

Figure 3 is a schematic diagram of an amplifier device of a second

embodiment of the present invention; Figure 4 is a schematic diagram of an amplifier device of a third embodiment of the present invention; Figure 5 is a schematic diagram of a Class D amplifier architecture of one embodiment of the present invention;

Figure 6 is a schematic diagram of an amplifier device according to a further embodiment of the present invention; and

Figures 7a to 7d are a graphical representation of the output signals from the comparators and amplifiers of the embodiment of Figure 5.

Turning to Figure 1 , there is shown a general schematic diagram of one embodiment of an amplifier device of the present invention, generally indicated as 2. The amplifier device 2 comprises a first amplifier assembly 4 for receiving an input signal to be amplified. The first amplifier assembly is a low power, linear amplifier, providing amplification of the input voltage signal, with only a low current output. The first amplifier assembly 4 may be any suitable amplifier or combination of amplifiers, in particular one or more Class A or Class A/B amplifiers, of known configuration. An alternative configuration for the first amplifier assembly 4 is shown in Figures 3 and 4, discussed in more detail hereinafter. The output of the first amplifier assembly 4 is split at a node 6. Signal output from the first amplifier assembly 4 is applied to the input of a second amplifier assembly 8. The second amplifier assembly 8 is a Class D amplifier, described in more detail below. The Class D amplifier is operable at higher input signal strengths and provides a high current output signal.

Signal output from the first amplifier assembly 4 is combined with the output from the second amplifier assembly 8 at a node 10, with the combined signal forming the amplified output signal from the amplifier device 2. This may be applied to a load, such as a speaker, in known manner. In operation, at low input signal strengths, the first amplifier assembly 4 provides the amplified signal to the output. The first amplifier assembly 4 is a linear amplifier, capable of accurately reproducing the input signal. At higher input signal strengths, the second amplifier assembly 8 operates to provide a high current output signal. The output signal of the first amplifier assembly 4 is applied to the node 10 through resistor R. Similarly, the output signal of the second amplifier assembly 8 is applied to the node 10 through an inductor L. The combined output signal is applied to the output of the device via a capacitance C, as shown in Figure 1. The operation of the first and second amplifier assemblies 4, 8 may be balanced by appropriate selection of the impedances R, L and C at the frequencies of operation of the device. The operation frequencies are preferably audio frequencies. In particular, it is preferred that the impedance R is at least 100 times greater than the sum of the impedances L and C, more preferably at least 200 times, still more preferably at least 500 times. A preferred arrangement is one in which the impedance R is about 1000 times the combined impedance of L and C.

One or more feedback loops 12 may be provided to apply feedback to the first amplifier assembly through an appropriate impedance. The second amplifier assembly 8 is preferably operated with feedback, as described in more detail hereinafter. Preferred feedback arrangements for both the first and second amplifier assemblies are shown in Figure 6 and described in more detail below.

Turning to Figure 2, there is shown one configuration of Class D amplifier for use as the second amplifier in the device of Figure 1. The amplifier, generally indicated as 20, is of known configuration and comprises a comparator 22, to which is applied the analogue input signal and a triangular reference signal generated by an appropriate signal generator 24. The comparator 22 generates a pulse width modulated (PWM) output signal, which is applied to a switching controller and output stage 26, the output of which is applied to a low pass filter (LPF) 28, to produce an amplified analogue signal as output from the amplifier.

A feedback loop may be provided for the amplifier 20. A crude feedback loop applies a signal from the output of the LPF 28 to the input of the comparator 22. A more efficient feedback arrangement applies a digital signal generated from the output of the LPF 28 using an analogue-to-digital converter.

Turning to Figure 3, there is shown a first preferred embodiment of the amplifier device of the present invention, generally indicated as 30. The device 30 has the general configuration shown in Figure 1. Thus, a signal to be amplified is applied to the input of a first amplifier assembly, generally indicated as 32. An output from the first amplifier assembly 32 is applied to the input of a second amplifier assembly 34. The second amplifier assembly 34 is a Class D amplifier having the configuration described above or hereinafter. Outputs from both the first amplifier assembly 32 and the second amplifier assembly 34 are combined at a node 36, to provide an amplified output signal. This output signal is shown in Figure 3 being applied to a speaker 38. The first amplifier assembly 32 comprises the following configuration. A first low power linear amplifier 40, for example a Class A amplifier, has the input signal applied to it. The output of the linear amplifier 40 is taken as a first output from the first amplifier assembly 32 and applied to the input of the second amplifier assembly 34, as shown in Figure 3. The output of the linear amplifier 40 is also applied to a further amplifier 42, the output of which is taken as a second output from the first amplifier assembly 32 and combined with the output of the second amplifier assembly 34 at the node 36. The amplifier 42, as represented in Figure 3, has the general configuration of a current dumping amplifier, for example as disclosed in US 3,970,953. The current dumping amplifier arrangement provides for a further level of amplification of the first amplifier 40. However, at very low loads, the current dumping amplifier has no bias at its output stage and the signal output by the first amplifier assembly 32 is that of the first amplifier 40. Other configurations for the amplifier 42 may also be employed. Turning now to the configuration of the second amplifier assembly, indicated as amplifier 8 in the general scheme of Figure 1 , as noted above the second amplifier assembly may be a known Class D amplifier. The schemes of Figures 1 and 3 indicate a single Class D amplifier as the second amplifier assembly 8, 34. Figure 4 shows a further embodiment of the amplifier device of the present invention. The device has the same general configuration as that of Figure 1 and components common to the two embodiments have been indicated using the same reference numerals. In Figure 4, there is shown an alternative arrangement, in which the second amplifier assembly comprises a Class D amplifier 8 having a plurality of output stages 8a to 8d arranged in parallel. The output stages are controlled by a single comparator and a single switching controller, generally indicated as 9, at the input of the amplifier 8. The switching controller comprises suitable logic devices for the selection and control of one of more of the output stages 8a to 8d. The output stages 8a to 8d of the second amplifier assembly 8 are operated out of phase, with their outputs being combined and summed to provide the output of the second amplifier assembly 8 applied at the node 10. In particular, at low loads, the switching controller operates the plurality of output devices in succession, thus distributing the duty across the devices present. At higher loads, two or more of the output devices are operated concurrently.

Figure 4 shows four output stages 8a to 8d arranged in parallel to form the second amplifier 8. It is to be understood that the number of amplifiers arranged in parallel in this manner may be fewer or greater than four, depending upon the load requirements of the device and the type of components being used.

A preferred architecture for the Class D amplifier of the second amplifier assembly is shown in Figure 5. In particular, there is shown the configuration of the input assembly for a Class D amplifier, generally indicated as 102. The input assembly 102 comprises a first comparator 104 and a second comparator 106. Each of the first and second comparators 104, 106 has an input signal applied at its input, through resistive loads 108a and 108b. The input signal is applied to each comparator 104,106 with a fixed reference voltage centred at zero volts. The reference voltages for the comparators 104, 106 are offset from each by 0.1 v. In operation, the input signal applied to the comparators moves the reference voltages from zero, but the inputs to the comparators 104, 106 retain their offset from each other. At input voltages less than the offset voltage, that is less than 0.1v, no load is applied to the amplifier, which has zero output signal. The offset voltage thus acts as a threshold for the input signal strength above which the amplifier is turned on and a load is applied to the output stages.

The output of the comparators 104, 106 is applied to a switching controller 110 comprising suitable logic devices for controlling one or a plurality of output stages 112. The output of the output stages is combined and applied to a low-pass filter (LPF) 114.

Further, a feedback signal is applied to each comparator, again through a resistive load 116a and 116b. The feedback signal is sourced from the output of the switching controller and output stage of the amplifier, at the output side of the LPF 114.

In contrast to the known configuration of Class D amplifiers, shown in Figure 2 and discussed above, in which the input signal and a reference triangular wave are applied to the comparator, the comparators 104, 106 of this embodiment of the invention operate on the offset input signals and the feedback signal.

In operation, the output stages of the amplifier are operated in a particularly efficient manner by the comparators 104, 106. The output stages generally each comprise at least one pair of output devices, typically MOSFETs, operated by the switching controller in response to the signals received from the comparators 104, 106. The output of the comparators 104, 106 is such that the switching controller operates just one of the pair of output devices to reproduce the applied signal. This operation is represented graphically in Figures 7a to 7d. Figure 7a shows signal output by an amplifier device having the general configuration shown in Figure 3 and employing a Class D amplifier as shown in Figure 5 as the second amplifier assembly. Figure 7b shows the output signal of the second amplifier assembly.

Figures 7c and 7d show the output signals of the comparators 104, 106 of Figure 5. The signals shown in Figures 7a to 7d were generated using the aforementioned arrangement and a sine wave as a representative input signal. As can be seen from Figures 7c and 7d, the positive phases of the input signal are reproduced by the activation of just one output device, while the negative phases of the input signal are reproduced with just the second output device. In each case, the input signal is reproduced by a series of pulsed operations of the respective output device at full load, with the pulse width varying. This is in contrast to conventional Class D amplifier architecture, which relies upon the use of both output devices throughout all phases of the input signal.

In the device of the present invention, as shown in Figures 7c and 7d, as the input signal swings past zero, both output devices are off. This is also visible in

Figure 7b, with the signal output by the second amplifier assembly having a flattened portion in the region of the signal crossing the zero axis. Again, this is in contrast to the conventional Class D amplifier architecture, in which a zero signal is reproduced by the pulsed operation of both output devices. The output signal of the device as shown in Figure 7a, is a sum of the signals output by the first and second amplifier assemblies. As noted above, in the region of the signal passing through zero, the second amplifier assembly ceases to operate, allowing the first amplifier assembly to provide the full output signal. In this way, the output remains stable and accurate in the region of the zero axis, as shown in Figure 7a.

Turning to Figure 6, there is shown a further preferred embodiment of the amplifier device of the present invention, generally indicated as 202. The device 202 has the general configuration shown in Figure 1. Thus, a signal to be amplified is applied to the input of a first amplifier assembly, generally indicated as 204. An output from the first amplifier assembly 204 is applied to the input of a second amplifier assembly 206. The second amplifier assembly 206 is a Class D amplifier having the configuration described above. Outputs from both the first amplifier assembly 204 and the second amplifier assembly 206 are combined at a node 208, to provide an amplified output signal.

The first amplifier assembly 204 comprises the following configuration. A first low power linear amplifier 210, for example a Class A amplifier, has the input signal applied to it. The output of the linear amplifier 210 is taken as a first output from the first amplifier assembly 204 and applied to the input of the second amplifier assembly 206, as shown in Figure 6. The output of the linear amplifier 210 is also applied to a further amplifier 212, the output of which is taken as a second output from the first amplifier assembly 204 and combined with the output of the second amplifier assembly 206 at the node 208.

Figure 6 shows details of arrangements for providing feedback to the amplifiers in the device. Thus, a local feedback loop 214 with an impedance 216 is applied around the first amplifier 210. Similarly, a local feedback loop 218 with an impedance 220 is applied around the second amplifier 212. A voltage proportioned local feedback loop 222 is applied to the second amplifier assembly 206.

A closing feedback loop 224 is applied around the linear amplifier stages within the first amplifier assembly 204 through an impedance 226. Finally, a closing feedback loop 228 around the total amplifier assemblies is applied through an impedance 230.

It is to be appreciated that one or more of the feedback arrangements shown in Figure 6 may be applied to the amplifiers within the device, as required for efficient operation.