Analog Combination Regulator

TECHNICAL FIELD

[0001] Various implementations relate to electrical systems.

BACKGROUND

[0002] Electronic systems that may use digital and/or analog circuits, such as microprocessors, for example, generally operate when supplied with a supply voltage. Many electronic systems are designed to operate from supply voltages that are regulated to provide a voltage that is within a range of voltage suitable for the circuitry.

[0003] Voltage regulators may generally include devices that have an input coupled to a power source and an output coupled to a load. In operation, a voltage regulator may draw energy from the power source and deliver energy to the load at a regulated voltage. Generally, the voltages of the power source and the load may be substantially independent of each other, an the voltage may be substantially different. In normal operation, the voltage regulator operates to supply current to the load at a voltage within an operating range of a nominal voltage. Some voltage regulators may be specified to regulate the voltage supplied to the load to within a tolerance of, for example, 1%, 5%, or 10% of the nominal voltage.

[0004] The nominal voltage that the regulator supplies to the load may depend on the type of load being supplied. In some digital systems, a voltage regulator may supply a nominal voltage of, for example, 3.3 Volts or 5 Volts. In some analog systems, a voltage regulator may supply a nominal voltage of, for example, -5 Volts,

2.5 Volts, 5 Volts, or 12 Volts. Many other tolerances and/or nominal voltages are possible.

[0005] Voltage regulators may be of various designs. For example, some switched mode dc-to-dc converters may produce a regulated output voltage by rapidly storing and releasing energy into and out of an energy storage element (e.g., inductor, capacitor). Examples of some switched-mode voltage regulator topologies include charge pumps, boost, buck, buck-boost, flyback, SEPIC, Cuk, and forward converters. Another type of voltage regulator is a linear regulator. Examples of linear regulators may include series pass and shunt regulators.

SUMMARY

[0006] Methods and apparatus may provide for multiple input voltage regulation in which a current supplied to an output node divides among voltage regulators according to their respective input voltages when the difference in input voltages falls within a voltage range. When the difference in input voltages falls outside of the voltage range, then the current to the output node is supplied substantially through the voltage regulator with the highest input voltage. In some implementations, the voltage range may be determined, at least in part, by a transistor gate-to-source threshold voltage characteristic. In one example, a dual input voltage regulator system in a combination smart card supplies current from contact and/or contactless (e.g., inductively coupled) power sources based on a relative voltage between the respective input voltages. [0007] Some implementations may provide one or more advantages. For example, some implementations may substantially mitigate potential misoperation

that may result from transient power conditions. As such, robust performance may be maintained during shifts in the relative strengths of available power sources. In some implementations, smooth transitions of current division among the regulators for each of a number independent power source inputs may substantially reduce or prevent, for example, data errors or other glitches. A single transistor drop architecture provides low drop-out voltage regulation capability without substantially increased transistor size. Some implementations may substantially prevent reverse current flow through regulators connected to inactive power inputs. In addition, low power operation may be achieved over a wide range of operating conditions by substantially reducing or preventing reverse (e.g., back feed) current flow through regulator transistors that are unselected or not coupled to active power sources. Performance may be enhanced in some implementations by selecting to draw electrical power from a highest available power source.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

[0009] FIG. 1 shows an exemplary system that includes a dual input voltage regulator that is configured to receive power from multiple power sources.

[0010] FIG. 2 illustrates an example of a dual input voltage regulator that is configured to transition between multiple power sources.

[0011] FIG. 3 is a graph showing an example of current transitioning as the voltage of one power source varies relative to another power source.

[0012] FIG. 4 shows a schematic of an exemplary circuit that implements a dual input voltage regulator using PMOS and NMOS transistors.

[0013] FIGS. 5A-B show exemplary implementations of a voltage selection module.

[0014] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION OF ILLUSTRATIVE EXAMPLES

[0015] FIG. 1 shows an exemplary system 100 that includes a dual input voltage regulator (DIVR) 105 that is configured to receive power from multiple (e.g., independent) power sources. The DIVR 105 receives input voltages Vl, V2 from input nodes 110, 115, respectively, and supplies an output current lout at a regulated voltage Vout to a device (e.g., processing system 120) at an output node 125. In one implementation, when Vl and V2 are within a circuit dependent window of each other, the DIVR 105 draws current from both input nodes 110, 115 to supply lout. When the difference between Vl and V2 falls outside of the window, the DIVR 105 draws current from the input node 110 or 115 with the highest voltage input Vl or V2, respectively, to supply lout. As such, the DIVR 105 may supply an output voltage Vout at the output node 125 with substantially reduced or eliminated transient effects, for example, as the input voltages Vl, V2 independently vary (e.g., turn on, turn off, strengthen, weaken).

[0016] In some implementations, the DIVR 105 may include a transistor that is operated to substantially block reverse current from the output node 125 to one of the input nodes 110, 115. For example, when the difference between Vl and V2 falls

outside of the circuit dependent window, reverse current flow to the input node 110,

115 with the lowest voltage input Vl, V2 may be substantially blocked.

[0017] The system 100 receives power from external sources 130, 135, which are coupled to the system 100 through interfaces 140, 145, respectively. In the depicted example, the system 100 receives power and/or data from the sources 130,

135. In some implementations, one or both of the interfaces 140, 145 may convert received data signals into power signals to supply operating power to the processing system 120. In some examples, either of the interface 140, 145 may include separate or integrated power and data ports for coupling to the corresponding sources 130,

135.

[0018] In the depicted example, the source 130 includes a power source 150 and a data interface 155, and the source 135 includes a power source 160 and a data interface 165. The power sources 150, 160 may transmit power to the system 100 through the interfaces 140, 145, respectively. The data interfaces 155, 165 may communicate with the system 100 by transmitting and/or receiving data through the interfaces 140, 145, respectively.

[0019] In various implementations, the interfaces 140, 145 may be configured to receive wired signals and/or wireless signals.

[0020] In some examples, the system 100 may receive power and data from a cable interface (e.g., via a universal serial bus (USB) interface). In some examples, the processing system 120 may communicate with either or both of the sources 130,

135 through the corresponding interfaces 140, 145.

[0021] Some implementations may be integrated in smart cards. In some implementations, smart cards send and/or receive data by communicating with an appropriate reader system. Some cards, commonly called contact cards, communicate with reader systems when the card makes direct electrical connection to a reader system. Data signals communicated over such direct contact interfaces may conform to a particular communication protocol, such as ISO/IEC 7816 or ISO/IEC 7810 (ISO refers to the International Organization for Standardization; IEC refers to the International Electrotechnical Commission). Other cards, called contactless cards, can communicate wirelessly with reader systems using RF (radio frequency) signals. RF data signals used by a contactless card may conform to a particular communication protocol, such as ISO/IEC 14443 or ISO/IEC 15693. [0022] Various types of power sources may supply the electrical power used to operate the circuitry in an integrated circuit card. For example, some cards are powered by an integrated power storage device, such as a battery or large value capacitor. Contact type cards can be powered by making direct electrical contact with terminals connected to a power source, which may be, for example, a power supply that is integrated in a reader system. Contactless type smart cards may be powered by capturing and storing radio frequency (RF) energy transmitted by a reader system. [0023] A hybrid type of smart card, sometimes called a combination card, can exchange data through either direct electrical contact or RF coupling to a reader system.

[0024] In an illustrative example, the interface 140 may be a contact interface, and the interface 145 may be a wireless interface. The contact interface 140 may

receive power from a primary battery, a secondary battery, and/or utility power. The wireless interface 145 may receive power by, for example, rectifying a received radio frequency (RF) signal such that the energy may be stored in a battery or capacitor. [0025] The voltage provided from the power sources 150, 160 may vary independently. For example, Vl may be supplied by a relatively stiff voltage source in a contact reader device, and Vl may appear to be turned on when contact is made with the interface 140 and turned off when contact is broken with the interface 140. V2 may be supplied through electromagnetic coupling to a contactless reader device. In this example, V2 may vary substantially depend on the orientation of the antenna with respect to the field, the distance from the transmitter, the presence or absence of field-distorting objects (e.g., metallic and/or lossy dielectric objects), signal reflections, humidity, and the like. Accordingly, V2 may vary among being less than, substantially near, or greater than Vl .

[0026] As such, the difference between Vl and V2 may sometimes be within the circuit dependent window (e.g., 0.2V, 0.3 V, 0.4V, 0.5 V, 0.6V, 0.7V, 0.8V, 0.9V, 1 V, etc.). Sometimes, the difference between Vl and V2 may be outside of the circuit dependent window. In one implementation, when Vl and V2 are within the window, the DIVR 105 draws power from both power sources 150, 160. When Vl and V2 are outside of the window, the DIVR 105 draws power substantially from the power source 150 or 160 supplying the highest voltage Vl or V2, respectively. [0027] In an illustrative example, the interface 140 receives battery power and the interface 145 receives RF power. Vl is initially constant and V2 is initially unpowered such that (V1-V2) is outside of a circuit dependent window. The DIVR

105 draws current substantially from the input node 110 to supply lout. Additionally, substantially no current flows through the input node 115. As RF field strength increases (e.g., when the interface 145 is brought substantially close to the RF source 135), V2 increases and, therefore, (Vl - V2) decreases. When (V1-V2) is within the window, the DIVR 105 supplies lout using current from both input nodes 110, 115. In certain implementations, the amount of current draw from the input nodes 110, 115 is directly related to Vl, V2. As the RF field strength continues to increase, V2 may become greater than Vl such that (V1-V2) is outside of the window. When (V1-V2) is outside of the window and V2 > Vl, the DIVR 105 draws current substantially from the input node 115. Examples of current transitions relative to the differences between Vl and V2 are described with reference to FIG. 3.

[0028] FIG. 2 illustrates an example of the DIVR 105 that is configured to transition current supplied by the power sources 150, 160 as their relative voltages vary. The DIVR 105 includes a transistor 205 to regulate voltage supplied from the input node 110, and a transistor 210 to regulate voltage supplied from the input node 115. The DIVR 105 produces the regulator output voltage Vout at the drain terminal of the transistors 205, 210, which are coupled to the output node 125. As shown in FIG. 2, the output current lout is supplied from either or both current paths indicated by the currents II, 12 through the transistors 205, 210. The currents II, 12 are controlled by the gate to source voltage (Vgs) of the transistors 205, 210. The supplied gate voltage is controlled such that lout is continuously supplied by Il and/or 12 during operation.

[0029] The DIVR 105 includes gate bias circuits 215, 220 to control gate voltages at the transistor 205 and the transistor 210, respectively. The gate bias circuits 215, 220 can regulate Vout by controlling the gate voltages. In the depicted example, the transistors 205, 210 are p-channel enhancement type metal-oxide- semiconductor field-effect transistor (PMOS). When Vgs is greater than a circuit dependent voltage threshold (Vt), the PMOS transistors 205, 210 may be turned off and may conduct substantially no current. When Vgs is less than Vt, the PMOS transistors 205, 210 may be turned on and may conduct a current from source to drain. In various implementations, Vt may depend on the type of transistors and other circuit elements. Typically, Vt of a PMOS transistor may range from, for example, about -4 V to about 0 V.

[0030] The gate bias circuits 215, 220 control the supplied gate voltages to allow transitions (e.g., smooth transitions) between the power sources 150, 160. The gate bias circuit 215 is supplied by voltage Vl, and the gate bias circuit 220 is supplied by voltage V2. In certain conditions, such as when Vl is approximately equal to V2, the gate bias circuits 215, 220 may supply substantially the same gate voltage to the transistors 205, 210.

[0031] The gate bias circuits 215, 220 may control Il and 12 based on the relative differences between Vl and V2. During operation, when either the voltage Vl or V2 is too low relative to the gate voltage to satisfy the threshold voltage condition (e.g., Vgs > Vt), then the corresponding current path is turned off. [0032] When both Vl and V2 are above the supplied gate voltage, the operation of the DIVR 105 depends on the relative difference between Vl and V2.

For example, when the voltages Vl and V2 are within the window, the transistors 205, 210 may allow the currents II, 12 to flow through the transistors 205, 210 to supply lout because Vgs is below Vt. Based on Vl and V2, the magnitude of the currents II, 12 vary. For example, when Vl is greater than V2, Il is greater than 12. When the voltages Vl and V2 are outside of the window, Vgs may be controlled such that lout is supplied substantially by the source 150 or 160 with the highest input voltage Vl, V2. For example, when Vl > V2, and Vl and V2 are outside of the window, lout is supplied substantially by the source 150.

[0033] The gate bias circuits 215, 220 generate the gate voltages based on a control signal Vbias received from an operational amplifier 225 and the voltages Vl, V2, respectively. The operational amplifier 225 receives a reference input and a feedback input at a node 230. The transistors 205, 210, the gate bias circuits 215, 220, and the operational amplifier 225 combine to form a feedback circuit to regulate Vout and control the currents II, 12 in the current paths. In certain implementations, the feedback circuit operates to control the Vgs of the transistors 205, 210 so that the DIVR 105 draws currents simultaneously from the input nodes 110, 115 when Vl and V2 are within the window, depending on Vout. Based on Vl, V2, and Vout, the feedback circuit generates gate bias voltages for the transistors 205, 210 to regulate Vout and to smoothly transition current flow through transistors 205, 210 as voltages of the power sources 150, 160 vary. When Vl and V2 are out of the voltage window, the feedback circuit may control Vgs at the transistors 205, 210 so that substantially all lout flows through the transistor coupled to the highest available input voltage Vl, V2.

[0034] FIG. 3 is an example graph 300 that illustrates current transitioning

(e.g., smoothly) as the voltage differential (V2 - Vl = δV) varies over a range. The graph 300 includes a horizontal axis 305 representing the quantity of δV and a vertical axis 310 representing the currents II, 12 through the transistors 205, 210 of FIG. 2.

[0035] In the graph 300, lines 315, 320 plot the characteristics of II, 12 over a range of δ V. In the DIVR 105, lout = Il + 12. In the example shown, Il and 12

change smoothly and continuously over the range of δ V. For example, there are no

abrupt discontinuities in the plots 315, 320. As such, lout is continuously supplied by at least one power supply. Accordingly, in some examples, the DIVR 105 may advantageously supply the output current lout with substantially reduced glitches. Particularly, in response to transitions in the input voltages Vl, V2. For example, when the power source 160 is removed suddenly from the system 100, forcing the DIVR 105 to transition from supplying current from the power source 160 to supplying current from the power source 150, the transition may occur smoothly with substantially reduced glitches.

[0036] As shown in FIG. 3, the graph 300 shows three regions of operations.

When δV is within the circuit dependent window between -VdI and Vd2, including -VdI and Vd2, the DIVR 105 operates in a region 1. When δV is less than -VdI, the DIVR 105 operates in a region 2a. When δV is greater than Vd2, the DIVR 110 may operate in region 2b.

[0037] When the DIVR 105 is operating in the region 1, the power sources

150, 160 may supply lout simultaneously. As shown in the graph 300, the DIVR 105

draws currents Il and/or 12 to supply lout. At δV = -VdI, the DIVR 105 may draw substantially only Il to supply lout such that Il is substantially equal to lout. As δV increases, 12 increases and Il decreases such that approximately Il+I2=Iout. At δV = Vd2, the DIVR 105 may draw substantially only 12 to supply lout such that 12 is substantially equal to lout. The window width is the range from -VdI to Vd2. In some examples, the VdI and Vd2 may be the same (e.g., |Vdl| = |Vd2| = 0.4 V). In other examples, the thresholds VdI, Vd2 of the power sources 150, 160 may not be symmetric. For example, VdI may be about 0.6 V and Vd2 may be about 0.4 V. VdI and Vd2 are and may be determined based on circuit dependent characteristics, such as gate to source thresholds of the transistors 205, 210. In an illustrative example, process parameter variations may contribute to variations of Vt (e.g., about +/- 100 mV). Various other factors may also contribute to window width. In some examples, Vt may increase as temperature decreases and/or as voltage from source to drain of a PMOS device increases. In addition, device matching may contribute to window width.

[0038] When the DIVR 105 is operating in the region 2a, the power source

150 supplies substantially all of lout and the current path coupled to the power source 160 supplies little or no current. In the depicted example, 12 is substantially zero but remains non-negative in the region 2a. When the DIVR 105 is operating in the region 2b, the power source 160 provides substantially all of lout and the current path coupled to the power source 150 supplies little or no current. In the depicted example, Il is substantially zero but remains non-negative in the region 2b.

[0039] As an illustrative example, suppose the DIVR 105 is regulating the output node 125 to 2.5V while supplying a load current of about 1.7 mA. Assume the power source 150 is supplying Vl to a substantially constant voltage 3.7 V, and V2 is ramping up from 0 V to 6 V. Initially, the DIVR 105 is operating in the region 2a. When V2 ramps up from 0 V to about (3.7 - VdI) V, the DIVR 105 continues to operate in the region 2a and substantially all lout is supplied from Il (e.g., Il is substantially 1.7 mA, and 12 is substantially zero and non-negative). When V2 and Vl are within the window (e.g., V2 is greater than (3.7 - VdI) V but less than (3.7 + Vd2) V), the DIVR 105 operates in the region 1 and lout is supplied simultaneously from Il and 12. In the example shown for the region 1, the contribution of Il decreases and the contribution of 12 increases as V2 increases. In various implementations, the sum of Il and 12 is substantially equal to lout while δV is in the operating region 1. As shown, the contribution of Il decreases smoothly (e.g., monotonically) and the contribution of 12 increases smoothly (e.g., monotonically) as V2 ramps up. In certain implementations, such as when Vl substantially equals V2, the power supplies 150, 160 share the load current substantially equally (e.g., Il = 12 = 850 μ A). When V2 is greater than (3.7 + Vd2) V, the DIVR 105 operates in the

region 2b and substantially all lout is supplied from 12 (e.g., 12 is substantially 1.7 mA, and Il is substantially zero and non-negative).

[0040] FIG. 4 shows a schematic of an exemplary circuit 400 that implements the DIVR 105 described with reference to FIG. 2. The circuit 400 shows the bias circuits 215, 220 and the operational amplifier 225 in additional detail. In some

implementations, the circuit 400 may be implemented using discrete and/or integrated components, or any combination thereof.

[0041] As described with reference to FIG. 2, the DIVR 105 regulates the output voltage Vout and supplies a current lout at the output node 125 and the DIVR 105 draws the currents II, 12 from the input nodes 110, 115, respectively. The transistors 205, 210 can control the currents II, 12 in the first and the second current paths, respectively, based on the gate voltage at the transistors 205, 210 supplied by the gate bias circuits 215, 220.

[0042] Under certain conditions, the gate bias circuits 215, 220 may supply substantially similar gate voltages to the gates of the transistors 205, 210. The gate circuits 215, 220 are supplied by voltages Vl, V2, respectively. As such, the gate bias supplied by each of the gate bias circuits 215, 220 may each depend on the corresponding supplied voltages Vl, V2. In the depicted example, the gate bias circuits 215, 220 are responsive to the control signal Vbias from the operational amplifier 225. Within the limits associated with the supplied voltage Vl, V2, in this example, the gate bias circuits 215, 220 may be responsive to Vbias to generate the gate voltages to the transistors 205, 210, respectively.

[0043] When the difference between Vl and V2 is within the window (e.g., the voltage region 1 in FIG. 3), the gate bias circuits 215, 220 are configured to allow Il and 12 to combine to supply lout. When the difference between Vl and V2 is outside of the window (e.g., the voltage regions 2a and 2b in FIG. 3), the gate bias circuits 215, 220 are configured such that substantially all lout is supplied through the

transistor 205, 210 that has its source coupled to the higher voltage as between Vl, V2.

[0044] The gate bias circuits 215, 220 can also regulate the output voltage

Vout using Vbias. To generate Vbias, the operational amplifier 225 uses a received feedback voltage and an input Vref. The received feedback voltage is directly related to Vout. According to Vref and the feedback voltage, the operational amplifier 225 outputs a voltage Vbias to the gate bias circuits 215, 220. Based on Vbias, Vl, and V2, the gate bias circuit 215, 220 allows currents II, 12 to supply lout, or enables only one current path to supply lout and substantially blocks reverse current. [0045] When only one of Vl, V2 is lower than a (e.g., circuit dependent) threshold, the operational amplifier 225 can control the gate bias circuits 215, 220 to substantially block current flow through that transistor 205 or 210. Factors that may affect a circuit dependent threshold include, but are not limited to, the characteristics (e.g., threshold voltage) of the transistors used to implement the gate bias circuits 215, 220 and the control voltage output by the operational amplifier 225. In an illustrative example, suppose the transistor 205 is switched off. The circuit 400 may substantially prevent reverse current flowing from the output node 125 to the input node 110 by turning off the transistor 205. As such, the output current lout is substantially supported by the current 12, and 12 does not supply a backfeed current through the transistor 205.

[0046] When both Vl and V2 are above the circuit dependent threshold, the gate bias circuits 215, 220 can control the currents Il and 12 flowing through the transistors 205, 210 using Vbias generated by the operational amplifier 225. The

current II, 12 may depend, for example, on whether the difference between Vl and V2 is inside or outside of the window.

[0047] If the difference between Vl and V2 is inside of the window, then the operational amplifier 225 may control the gate bias circuits 215, 220 to enable both current paths to conduct the currents II, 12 via the transistors 205, 210. If the difference between Vl and V2 is outside of the window, then the operational amplifier 225 may control the gate bias circuits 215, 220 to enable the current path with the highest voltage to substantially supply the current lout. The relative amplitudes of currents II, 12 may be directly related to the relative voltage Vl and V2. In some examples, for a particular differential voltage, the relative current division between the current paths may remain substantially constant as the load current varies. The ratio of currents II, 12 may vary over a range of voltage difference between Vl and V2, as shown in the graph 300. [0048] The circuit 400 also includes a voltage selection module 450 that selects a highest voltage between the supply voltages, Vl and V2. The voltage selection module 450 receives the supply voltages and generates an output voltage at a node Vselect. In the depicted example, the output voltage is supplied to body terminals of PMOS transistors of the bias circuits 215, 220. [0049] As Vl and V2 vary, the output voltage at Vselect may provide substantially the highest supply voltage available from the two supply voltages Vl, V2. The Vselect may provide substantially the highest available voltage to the body terminals of the PMOS transistors. For example, supplying the highest available voltage to the substrates of the PMOS devices may, for example, substantially reduce

or prevent unintentional forward bias of internal junctions in the PMOS transistors. Furthermore, Vselect may, in some implementations, contribute to reducing and/or preventing reverse current flow, for example, through a source-bulk of unused output PMOS devices. Some examples of the voltage selection module 450 are described in further detail with reference to FIGS. 5A-B.

[0050] FIGS. 5A-B show exemplary circuits 500, 550 that implement the voltage selection module 450. As shown in FIG. 5A, the circuit 500 includes two NMOS transistors 505, 510 connected to the voltage supplies Vl and V2, respectively. The circuit 500 may supply the higher of Vl and V2 to an output node Vselect. As described in an example with reference to FIG. 4, the Vselect voltage may be supplied to the substrates (e.g., body connection) of various PMOS transistors in the bias circuits 215, 220 and/or the transistors 205, 210, for example. In some implementations, supplying the highest available voltage to the PMOS substrates may substantially prevent unintentional forward bias of internal junctions in the PMOS transistors.

[0051] In some implementations, the NMOS transistors 505, 510 may have substantially zero Vt. In some implementations, the NMOS transistors 505, 510 may have a positive threshold voltage (e.g., Vt up to at least about 1 V). In some examples, Vds of the NMOS transistors 505, 510 may be directly related to Vt. A small Vt at the NMOS transistors 505, 510 may induce a small voltage drop across the drain terminals and the source terminals (Vds), for example. [0052] In operation, the voltage selection module 450 may select a highest voltage between Vl and V2 at Vselect. For example, suppose Vt is substantially 0 V.

When Vl > V2, the voltage at Vselect may be approximately Vl and the NMOS transistor 510 may be turned off because Vds at the NMOS transistor 510 (which is Vselect- V2) is less than Vt (which is substantially 0 V). When V2 > Vl, the voltage at Vselect may be approximately V2 and the NMOS transistor 505 may be turned off because Vds at the NMOS transistor 505 (which is Vselect-Vl) is less than Vt (which is substantially 0 V).

[0053] As shown in FIG. 5B, the circuit 550 includes PMOS transistors 555,

560. The circuit 550 may provide advantages, such as additional reverse current protection when using NMOS devices with a Vt of approximately 0, for example. In various implementations, PMOS devices may facilitate achieving reduced dropout voltage and/or reduced size.

[0054] Alternatively, other implementations of the voltage selection module

450 may be used. For example, a voltage selection module may be implemented to select a lowest input voltage as the output using PMOS with substantially zero Vt. [0055] Although an example of a system, which may be portable, has been described with reference to the above figures, other implementations may be deployed in other applications, such as other circuit applications, computing applications, network applications and the like.

[0056] In certain implementations, the system 100 may obtain power from more than two power sources. For example, using the same technique, the DIVR 105 may regulate Vout using three or more power sources. By controlling the gate voltage of each of the PMOS transistors that regulate the input voltages, the DIVR 105 may control current division among each of the power sources. When the input

voltages are out of a voltage range, the output power is supplied by a power source with the highest input voltage. Additionally, reverse current flow may be substantially prevented for each of the multiple sources by appropriate biasing of the corresponding transistors.

[0057] In implementations with more than two voltage regulators, various operating modes may be used. For example, the DIVR 105 may receive currents from more than two input nodes, such as three or more voltage inputs. Each input can be controlled by a gate bias circuit responsive to the Vbias signal generated from the operational amplifier 225. When more than one voltage is above the circuit dependent threshold, for example, the gate bias circuits may control the amount of current flowing through each current paths based on the relative voltage difference between the input voltages.

[0058] In some other implementations, current regulators may be substituted for voltage regulators, for example, by replacing the opamp circuit 225 (see FIG. 2) with a current comparator, and comparing a reference current with the delivered load current.

[0059] In some implementations, the DIVR 105 can be configured to use voltage supplies that are negative with respect to a circuit reference voltage (e.g., ground). For example, the DIVR 105 may use N-channel MOS transistors for such negative voltages. When the DIVR 105 is supplied by the negative voltages, the gate bias circuits 215, 220 may select an active current from the input nodes 110, 115 having the lowest (e.g., most negative) voltage when the difference between the input voltages are out of the window. When the difference between the input voltages are

inside of the window, the gate bias circuits 215, 220 may allow multiple (e.g., both) current paths to simultaneously support the output current. In some implementations, the linearity may be sufficient to substantially avoid dithering when operating in or around the edges of the window. In some implementations, a selective window feature could optionally be implemented to temporarily lock one of the regulators in its current state (e.g., to supply all the load current lout). Such an implementation may be advantages, for example, if the Vl source provides limited stability or poor disturbance rejection at an operating point around which V2 may operate. [0060] Although particular features of an architecture have been described, other features may be incorporated to improve performance. For example, other hardware and software may be provided to perform operations, such as network or other communications using one or more protocols, wireless (e.g., infrared) communications, stored operational energy and power supplies (e.g., batteries), switching and/or linear power supply circuits, software maintenance (e.g., self-test, upgrades). One or more communication interfaces may be provided in support of data storage and related operations.

[0061] Some systems may be implemented as a computer system that can be used with implementations of the invention. For example, various implementations may include digital and/or analog circuitry, computer hardware, firmware, software, or combinations thereof.

[0062] In various implementations, the system 100 may communicate using suitable communication methods, equipment, and techniques. For example, the system 100 may communicate with compatible devices (e.g., devices capable of

transferring data to and/or from the system 100) using point-to-point communication in which a message is transported directly from the source to the receiver over a dedicated physical link (e.g., fiber optic link, point-to-point wiring, daisy-chain). The components of the system may exchange information by any form or medium of analog or digital data communication, including packet-based messages on a communication network. Examples of communication networks include, e.g., a LAN (local area network), a WAN (wide area network), MAN (metropolitan area network), wireless and/or optical networks, and the computers and networks forming the Internet. Other implementations may transport messages by broadcasting to all or substantially all devices that are coupled together by a communication network, for example, by using uni-directional radio frequency (RF) signals. Still other implementations may transport messages characterized by high directivity, such as RF signals transmitted using directional (i.e., narrow beam) antennas or infrared signals that may optionally be used with focusing optics. Still other implementations are possible using appropriate interfaces and protocols such as, by way of example and not intended to be limiting, USB 2.0, Firewire, ATA/IDE, RS-232, RS-422, RS- 485, 802.11 a/b/g, Wi-Fi, Ethernet, IrDA, FDDI (fiber distributed data interface), token-ring networks, or multiplexing techniques based on frequency, time, or code division. Some implementations may optionally incorporate features such as error checking and correction (ECC) for data integrity, or security measures, such as encryption (e.g., WEP) and password protection.

[0063] A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without

departing from the spirit and scope of the invention. For example, advantageous results may be achieved if the steps of the disclosed techniques were performed in a different sequence, if components in the disclosed systems were combined in a different manner, or if the components were replaced or supplemented by other components. The functions and processes (including algorithms) may be performed in hardware, software, or a combination thereof, and some implementations may be performed on modules or hardware not identical to those described. Accordingly, other implementations are within the scope of the following claims.