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Title:
ANALOG SWITCHED-CAPACITOR NEURAL NETWORK
Document Type and Number:
WIPO Patent Application WO/2019/051354
Kind Code:
A4
Abstract:
Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Inventors:
NESTLER, Eric G. (2015 Waverly Avenue, Long Beach Township, New Jersey, 08008, US)
VERMA, Naveen (290 Hamilton Avenue, Princeton, New Jersey, 08540, US)
VALAVI, Hossein (17131 Avalon Way, Lawrenceville, New Jersey, 08648-1243, US)
Application Number:
US2018/050169
Publication Date:
May 02, 2019
Filing Date:
September 10, 2018
Export Citation:
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Assignee:
ANALOG DEVICES, INC. (One Technology Way, Norwood, Massachusetts, 02062, US)
TRUSTEES OF PRINCETON UNIVERSITY (Nassau Hall, Princeton, New Jersey, 08540, US)
International Classes:
G06N3/063; G11C11/412; G11C11/417
Attorney, Agent or Firm:
KARLSSON, Annika K. et al. (Patent Capital Group, 2816 Lago Vista LaneRockwall, Texas, 75032, US)
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Claims:
AMENDED CLAIMS

received by the International Bureau on 14 March 2019 (14.03.2019)

1. An apparatus for in-memory computing using charge-domain circuit operation, comprising: a first plurality of transistors configured as memory bit cells; a second plurality of transistors configured to perform in-memory computing using the memory bit cells; a plurality of capacitors configured to store a result of in-memory computing from the memory bit cells; and a plurality of switches, wherein, based on a setting of each of the plurality of switches, charges on at least a portion of the plurality of capacitors are shorted together; wherein shorting together the plurality of capacitors yields a computation result.

2. The apparatus of claim 1, wherein the first plurality of transistors is configured to store a plurality of matrix values.

3. The apparatus of claim 2, wherein the second plurality of transistors is configured to receive an input signal, perform analog charge-domain computations using the input signal and the plurality of matrix values, and generate the result of in-memory computing.

4. The apparatus of claim 1, wherein the plurality of capacitors are positioned above the first plurality of transistors and the second plurality of transistors.

5. The apparatus of claim 1, wherein the plurality of capacitors are formed from a dielectric between interconnect layers in a VLSI technology.

6. The apparatus of claim 1, wherein the apparatus is configured to be placed in a neural network.

7. The apparatus of claim 1, wherein the first plurality of transistors are configured as one of single memory bit cells and multiple memory bit cells.

8. A circuit for matrix-vector computations, comprising: a plurality of bit cell portions configured to store matrix elements, receive broadcast vector elements, perform compute operations, and generate bit cell outputs; a plurality of capacitors configured to store the bit cell outputs from the plurality of bit cell portions; and a plurality of switches, wherein, in a first switch configuration, charge from at least a portion of the plurality of capacitors are shorted together.

9. The circuit of claim 8, wherein the circuit is configured to perform matrix-vector multiplication operations.

10. The circuit of claim 8, wherein the compute operations include logic operations.

11. The circuit of claim 8, wherein the plurality of capacitors are positioned above the plurality of bit cell portions.

12. The circuit of claim 8, wherein the plurality of bit cell portions are configured as one of single memory bit cells and multiple memory bit cells.

13. The circuit of claim 8, wherein the plurality of bit cell portions each include a plurality of transistors. 14. A method for matrix-vector computation, comprising: storing 1-bit matrix elements locally in a compact circuit structure;

broadcasting 1-bit vector elements to the matrix elements;

storing charge on a plurality of capacitors to locally perform a computation; and

accumulating charge from each of the plurality of capacitors by shorting together charge from the plurality of capacitors. 36

The method of claim 14, further comprising performing analog charge domain computations using the 1-bit matrix elements and the 1-bit vector elements.

The method of claim 14, wherein the compact circuit structure includes a plurality of transistors, and further comprising receiving an input signal at the plurality of transistors.

The method of claim 14, further comprising:

discharging the plurality of capacitors, wherein discharging results in the charge on each of the plurality of capacitors having a logic value of zero; and

conditionally charging each of the plurality of capacitors, based on a respective matrix element and a respective vector element.

18. The method of claim 17, wherein discharging the plurality of capacitors further comprises:

closing a first plurality of switches, wherein each switch of the plurality of switches is coupled to a corresponding capacitor of the plurality of capacitors, and activating a discharge transistor.

19. The method of claim 14, wherein accumulating charge from each of the plurality of capacitors results in generating an analog pre-activation value.

20. The method of claim 14, further comprising closing a plurality of first switches to cause the charge from each of plurality of capacitors to short together, wherein each of the plurality of first switches is connected to a respective capacitor from the plurality of capacitors.