ANALOG-TO-DIGITAL CONVERTER TIMING CIRCUITS

BACKGROUND Technical Field:

[0001] This disclosure generally relates to analog-to-digital converters and more specifically to sub-quantizer architectures for analog-to-digital converters.

Description of the Related Art:

[0002] Common design architectures for analog to digital converters (ADCs) are the so-called "pipelined architectures." For many applications, a pipelined architecture scheme is preferable because it provides optimum power dissipation characteristics. In addition, there are other available architectures that resemble a pipelined architecture because the same principle building blocks are employed.

[0003] FIG. 1 illustrates a typical pipelined ADC. The architecture consists of several pipeline stages, each resolving a number of bits. The number of bits can be different for each stage, but for simplicity of explanation, all stages are considered equal. The input signal is applied to the first pipeline stage. A number of bits are extracted in the first stage by the sub-ADC, the input signal is sampled in parallel and the analog value corresponding to the output bits is subtracted from the input voltage. The residual signal, called the "residue," is amplified with a factor dependent on the number of bits extracted and passed on to the next stage. The process is repeated in the consecutive stages. The digital output from each stage is processed in a digital correction logic block and combined into an n-bit output data word.

[0004] Several prior art techniques have been used to improve power dissipation of pipelined ADCs. The two papers explain a technique that is shown to significantly reduce power

dissipation: (1) Gupta et al, A IGS/s lib Time-Interleaved ADC in 0.1 Sum CMOS, 2006 Digest of Technical Papers, ISSCC 2006, session 31.6; and (2) Vital et al., A Concurrent Two-Step Flash Analogue-To-Digital Converter Architecture, ISCAS apos; 93, 1993 IEEE International Symposium, May 3-6, 1993, pp. 1 196-1199, vol. 2.

[0005] These papers disclose a technique wherein the operational transconductance amplifiers (OTA) are shared between the several stages of the ADC. In an ordinary pipelined ADC implementation, the OTA is used only half of the time and is active for only half of each clock cycle. By sharing the OTA between two pipeline channels running in antiphase, or in opposite phases with one another, the OTA can be utilized all the time. Using the OTA all the time results in significant power dissipation savings. The principle of OTA sharing is shown in Gupta et al. while an actual implementation of a shared OTA is shown in Vital et al. This architecture that features OTA sharing is commonly called an "interleaved ADC."

[0006] FIG. 2 shows an implementation of a single pipeline stage according to the interleaved ADC solution explained in Gupta and Vital. In this implementation, the ADC consists of two parallel channels implemented in each pipeline stage. The inputs to the two channels are shorted such that the same signal is propagated through each channel. Alternatively, the two channels could be kept separate, implementing two parallel independent channels. The channels work in antiphase such that one channel is in hold mode when the other channel is in sampling mode.

[0007] The operation of the prior art technique of OTA sharing implemented in a pipeline stage is as follows. The input signal to the stage is applied to two channels, 100 and 101. When the channel 100 starts in track-mode and channel 101 is in hold-mode, the input signal is applied to the sub- ADC 1 of channel 100 in parallel to a sampling network. The sub-ADC 1 quantizes the input signal and outputs N bits at the end of the track-phase. These N bits are converted back to

an analog voltage by the DAC 2, to be used in the hold-phase. During the track-phase, all switches labeled "T" are closed. These switches are opened at the end of the track -phase sampling the input voltage on the sampling capacitors Cs and C _H - In the hold-phase, the switches labeled "H" are closed. This closes the loop around the amplifier comprising of the OTA input stage 3 and the OTA output stage 4, and the input voltage is amplified and held on the stage output terminal. The DAC output voltage is also subtracted from the output through the capacitive feedback network of Cs and C _H - This functionality is equal to an ordinary pipeline stage.

[0008] When the channel 100 is in the track-phase, the channel 101 may be in hold-phase. When the two channels switch phases, the OTA output stage 4 switches operation from one channel (e.g. 100) to the other (e.g. 101). Therefore, the OTA output stage 4 is active 100% of the time while it is idle during the track-phase of an ordinary pipeline stage. In FIG. 2, the OTA input stages 3, 3a will be idle during the track-phase of their respective channels 100, 101. However, in a typical implementation, most of the current from both channels 100, 101 flows through the OTA output stage 4, thereby providing the benefit of sharing the OTA output stage between the two channels 100, 101.

[0009] To further reduce power dissipation, it is possible to switch off the current in the OTA input stages 3 or 3a when the respective channel 100, 101 is in the track-phase. This would typically be implemented as a fixed bias current that is steered to one of the OTA input stages 3, 3a based on the clock signals controlling whether the channel 100, 101 is in track-phase or hold- phase. This would result in a bias current that is half of the bias current of a traditional solution.

[0010] A major challenge using such an OTA sharing principle is the generation of the necessary timing pulses for correct operation and accurate clocking of the pipeline stages. For

high resolution ADCs, it is critical to generate a sampling clock with sufficiently low phase noise or equivalent clock jitter. In addition, in typical pipelined ADCs, the input clock may have exactly 50% duty cycle in order for the ADC to have full performance.

[0011] Therefore, there is a need for new timing circuits with specific characteristics to use with the architectures described above.

SUMMARY OF THE DISCLOSURE

[0012] A disclosed timing circuit includes a clock input, two output terminals two flip-flops, four logic NOR gates, two logic AND gates and an inverter. The first flip-flop may be connected with its inverting output back to the input of both the first and the second flip-flop. The non- inverting output of the first flip-flop may be connected to the first input of the first NOR gate and the clock input may be connected to the second input of the NOR gate.

[0013] The output of the first NOR gate may be connected to the first input of the second NOR gate. The inverting output of the second flip flop may be connected to the first input of the first AND gate. The clock input may be connected to the second input of the first AND gate. The output of the AND gate may be connected to the second input of the second NOR gate. The non- inverting output of the second flip-flop may be connected to the first input of the second AND gate, and the clock input may be connected to the second input of the second AND gate. The output of the second AND gate may be connected to the second input of the fourth NOR gate. The inverting output of the first flip-flop may be connected to the first input of the third NOR gate. The clock input may be connected to the second input of the third NOR gate. The output of the third NOR gate may be connected to the first input of the fourth NOR gate. The clock input may be connected to the clock input of the first flip-flop and to the input of the inverter.

[0014] The output of the inverter may be connected to the clock input of the second flip-flop. The output of the second NOR gate may be connected to the first output terminal and the output of the fourth NOR gate may be connected to the second output terminal. The first and the second output terminals are utilized in an interleaved analog-to-digital converter such that only rising edges of the input clock may be utilized for analog circuitry. As a result, the analog-to-digital converter can be insensitive to input clock duty cycle. Further, a minimum clock jitter may be added to the clock signal while it is propagating through the disclosed circuit.

[0015] Thus, a method of clocking of an interleaved pipelined converter is disclosed wherein only one edge of the input clock may be used to control analog circuitry of the interleaved pipelined converter.

[0016] Other advantages and features will be apparent from the following detailed description when read in conjunction with the attached drawings.

BRIEF DESCRIPTION QF THE DRAWINGS

[0017] For a more complete understanding of the disclosed methods and apparatuses, reference should be made to the embodiments illustrated in greater detail in the accompanying drawings, wherein:

[0018] FIG. 1 illustrates a typical block diagram of a prior art pipelined ADC;

[0019] FIG. 2 schematically illustrates a block diagram of a prior art solution for a pipeline stage where the OTA is shared between stages in parallel pipeline chains;

[0020] FIG. 3 illustrates a disclosed timing diagram that illustrates the necessary clocks for operation independent of the input clock duty cycle; and

[0021] FIG. 4 illustrates a timing generation circuit and a corresponding timing diagram.

[0022] It should be understood that the drawings are not necessarily to scale and that the disclosed embodiments are sometimes illustrated diagrammatically and in partial views. In certain instances, details which are not necessary for an understanding of the disclosed methods and apparatuses or which render other details difficult to perceive may have been omitted. It should be understood, of course, that this disclosure is not limited to the particular embodiments illustrated herein.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0023] A method and system are disclosed to clock an interleaved pipelined ADC such that the operation is insensitive to input clock duty cycle and such that the clock jitter on the sampling clock edges is minimized.

[0024] As shown in FIG. 3, the input clock CLK to the ADC is a clock running at the sample rate similar to a prior art pipelined ADC. Half rate clock signals may be generated because each of the channels is running at half the clock rate. These divided down clocks are shown as CK CH 1 and CK_CH 0 in FIG 3. These clocks may be used internal to each pipeline stage to generate local control signals for the T and H switches of FIG 2. The "T" and "H" labels on the CK_CH 1 and CK_CH 0 signals in FIG 3 indicate whether the channel is in track mode ("T") or hold mode ("H"). Note that the edges of these signals only exist on rising edges of the input clock. The sub- ADC 1 and sub- ADCO are also latched on the clock edges of CK CH 1 and CK_CH 0, as shown in FIG 3. As each channel goes from track-mode to hold-mode, latch signals are sent to the sub- ADC 1 or sub-ADCO and the respective channel goes from the reset-phase to the valid-data-phase. The sub-ADC 1 and sub-ADCO are regenerative elements, and the time taken from the latch pulse

is applied until valid data are ready at the output, depends on the input voltage. This is shown in FIG 3 as a delay between the reset-phase and valid-data-phase. There are also latches L behind the sub-ADC 1 and sub-ADCO that are open (transmitting the input signal directly through) when the respective CK_CH 1 or CK_CH O signal is low, and holding the output data when the respective CK_CH 1 or CK_CH 0 signal is high. This gives output data for each channel that are valid for almost the complete clock period of the channel.

[0025] Still referring to FIG. 3, the only signal working on the negative edge of the input clock is the channel select signal, CHSEL. The CHSEL signal is used to control multiplexers delivering the digital data from the sub-ADCs (sub-ADC 1 and sub-ADCO) to the digital logic block. When CHSEL is low, data from channel 0 (Data 0) is sent to the stage output and when it is high, data from channel 1 (Data 1) is sent to the stage output as shown in FIG 3. The digital logic block of the pipelined ADC will be running at the full clock rate from the clock signal CLK, The digital logic block will capture data at the rising edge of CLK. These rising edges will typically be in the center of the valid period of Data 0 and Data 1.

[0026] In case of an input clock duty cycle different from 50%, the only thing that will happen is that the valid periods of Data 0 and Data 1 are moved back and forth. It is almost half a clock cycle margin both at the LATCH OUT output and at the input of the digital logic block. The clocking scheme shown is therefore very insensitive to changes in clock duty cycle which is a significant advantage over prior art pipelined ADCs.

[0027] Because the sampling instant of the ADC is determined by the clocks CK_CH 1 and CK_CH 0, it is necessary to generate these with as high accuracy and low clock jitter as possible. Any clock jitter added to the input clock will reduce the obtainable performance of the ADC. In standard clock dividers, the clock edge is typically generated through a flip-flop. The signal path

of a flip-flop contains several circuit elements, and the transmission delay is relatively long. These two aspects, among others, make the design of very low jitter clock generation circuitry difficult.

[0028] The clock generation circuit shown in FIG 4 solves this problem. All clock outputs have only two logic elements in the signal path from the main clock input to each of the CK_CH 1 and CK CH 0 outputs. The functionality of the circuitry in FIG 4 is as follows:

[0029] The top flip-flop 400 in FIG 4 divides down the input clock frequency to half the rate. The Q and QN outputs from the flip-flops are non-inverting and inverting outputs respectively. Each of the four flip-flop outputs set up enable signals for the logic gates without making any changes in the output signals CK_CH 1 and CK_CH 0. The signals for all nodes are shown in FIG 4. As soon as the input clock changes polarity, both output signals change within the delay represented by the logic gates, and the flip-flop delay is negligible. The result is that the CK_CH 1 and CK CH 0 signals change prior to CKENl and CKEN 1_N. In this way the contribution to clock jitter is minimized from this clock circuit. Only two logic elements, and no flip-flop, are part of the path for the clock through the circuit.

[0030] The delays through the logic gates may be dimensioned such that the output signals CK_CH 1 and CK_CH 0 are glitch free. This can be achieved, for example, by ensuring that the delay through the AND gates 402 ad 403 is larger than the delay through the NOR gates 404 and 405. This can also be verified by studying the waveforms of FIG 4.

[0031] Alternatively, the disclosed clock generation circuit may be used in subranging ADCs. Further, the clock generation circuit described above may be used in cyclic ADCs.

[0032] While only certain embodiments have been set forth, alternatives and modifications will be apparent from the above description to those skilled in the art. These and other alternatives are considered equivalents and within the spirit and scope of this disclosure and the appended claims.