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Title:
ANALOG-TO-DIGITAL CONVERTER TIMING CIRCUITS
Document Type and Number:
WIPO Patent Application WO/2009/090496
Kind Code:
A3
Abstract:
An analog-to-digital converter timing circuit disclosed herein uses a clock generation circuit that makes the analog-to-digital converter insensitive to input clock duty cycle. Minimum clock jitter is added to the clock signal while propagating through the disclosed circuit. A method and system are also disclosed to clock an interleaved pipelined ADC such that the operation is insensitive to input clock duty cycle and such that the clock jitter on the sampling clock edges is minimized.

Inventors:
HERNES BJORNAR (NO)
TELSTO FRODE (NO)
ANDERSEN TERJE NORTVEDT (NO)
Application Number:
PCT/IB2008/003947
Publication Date:
August 11, 2011
Filing Date:
December 10, 2008
Export Citation:
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Assignee:
ARCTIC SILICON DEVICES AS (NO)
HERNES BJORNAR (NO)
TELSTO FRODE (NO)
ANDERSEN TERJE NORTVEDT (NO)
International Classes:
G06F1/04; H03K5/151; H03K5/156
Foreign References:
US6246278B12001-06-12
US20030020554A12003-01-30
US5249214A1993-09-28
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