FIG. 1 shows the architecture of a pipelined analog to digital converter (ADC) with a front- end sample and hold stage (SHA) (shown as S/H in diagram) followed by k stages each resolving 2 bits (nl = 2). Also shown are the basic building blocks of a typical stage.

One of the general methods used to reduce power consumption of a pipelined ADC design is by removing the SHA at the input before the first stage. Traditionally, a SHA stage is widely used in the front end of a converter to provide a stable direct current (DC) input to the following stage. The SHA stage achieves this by minimizing the aperture error caused by the mismatch that commonly occurs between the first stage multiplying digital-to-analog converter (MDAC) and the comparators in the sub-ADC of the first stage. The SHA usually has large power dissipation and contributes substantially to the distortion and noise of the entire ADC, as such, removing them is advantageous.

When the SHA removed, it is then more crucial to match the time constant between the two signal paths (i.e. the sub-ADC path and the MDAC path). The conventional way of implementing this is by using comparator designs in the sub-ADC blocks with pre-amplifiers and latches.

A pipeline analog to digital converter, which does not have the SHA, which is dynamic in operation (i.e. pre-amplifier-less), and which is able to match the time constant between the signal paths of the sub-ADC and the MDAC, is therefore very much needed. SUMMARY OF THE INVENTION

Accordingly, there is provided an analog to digital converter (ADC) (100). The ADC is comprised of a quantizer component for sampling an incoming analog signal and for generating a digital signal; and a residue generator component for sampling the incoming analog signal and for generating a residual analog signal with respect to the digital signal.

The quantizer component is switchably connected to a source of incoming analog signals. The quantizer component is also comprised of a comparator circuit having a plurality of first transistors for substantially acting as voltage-controlled resistors therein, and a plurality of second transistors for substantially forming a latch therein. The comparator circuit is also of a dynamic type wherein no pre-amplifier is used therein. The residue generator is switchably connected to the source of the incoming analog signals. The input of the residue generator component is also connected to the output of the quantizer component. It is essential that the comparator circuit and the switchable connection are for matching the sampling characteristics of the quantizer and the residue generator components. It is a first object of the present invention to provide a pipelined analog to digital converter that does not require a sampling (sample and hold) circuit in the front end of the first stage of the pipeline to reduce the power consumption thereof, to lower the distortion and the noise thereof, and to further simplify the architecture of the ADC. It is a second object of the present invention to provide a dynamic comparator circuit in the quantizer component to match the sampling characteristics of the quantizer and the residue generator components. To this end, the aperture errors associated with the residual analog signals are eliminated. The accuracy of the ADC circuit in generating residual analog signals is further increased. It is a third object of the present invention to provide a dynamic comparator circuit in the quantizer component. The facts that no pre-amplifier is used in the comparator circuit and the comparator circuit only dissipates power during a latched state contribute to power reduction. No pre-amplifier being used also simplifies the architecture of the subtractor ADC (sub- ADC).

It is a fourth object of the present invention to eliminate the kickback noise from the latch (of the dynamic comparator) to the residue generator by de-coupling the comparator circuit from the residue generator component.

It is a final object of the present invention to eliminate the need for the reference sampling capacitors in the residue generator component such that larger feedback factor is yielded and the power consumption is further reduced. The present invention consists of certain novel features and a combination of parts hereinafter fully described and illustrated in the accompanying drawings and particularly pointed out in the appended claims; it being understood that various changes in the details may be without departing from the scope of the invention or sacrificing any of the advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

For the purpose of facilitating an understanding of the invention, there is illustrated in the accompanying drawings the preferred embodiments from an inspection of which when considered in connection with the following description, the invention, its construction and operation and many of its advantages would be readily understood and appreciated.

FIG. 1 shows a conventional pipelined analog to digital converter (ADC) architecture.

FIG. 2 shows an exemplary architecture of a single stage of a pipelined ADC. FIG. 3 shows an exemplary architecture of a single stage of a pipelined ADC with the inclusion of a front-end sample and hold S/H stage.

FIG. 4 shows a conventional ADC design of a prior art.

FIG. 5 shows a circuit diagram for a flash comparator used in the prior art.

FIG. 6 shows a circuit diagram for a flash comparator circuit used in the present invention. FIG. 7 shows a dynamic comparator of the present invention that is inserted into a conventional prior art topology.

FIG. 8 shows a sampling mismatch that occurs between the comparator circuit block and the (Multiplying Digital-to-Analog Converter (MDAC)) block.

FIG. 9 shows a topology used with a dynamic comparator circuit of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an analog to digital converter (ADC) 100. Hereinafter, the ADC 100 shall be described according to the preferred embodiments of the present invention and by referring to the accompanying description and drawings. However, it is to be understood that limiting the description to the preferred embodiments of the invention and to the drawings is merely to facilitate discussion of the present invention and it is envisioned that those skilled in the art may devise various modifications without departing from the scope of the appended claim.

Referring to FIG. 2, the architecture of a single stage of a prior art pipelined ADC 10 is shown. The ADC is usually implemented in a circuit form that uses comparators for the sub- ADC block 14 and a multiplying digital-to-analog converter MDAC block 16. An input signal Vin is applied to the input node 12. Within the stage, this node is connected to the input of a quantizer 14 and a (usually switched capacitor) residue generator 16. The quantizer is typically an analog-to-digital converter such as a flash converter. The output of the quantizer 14 is a digital representation of the input signal, which is usually consisted of only a few bits resolution. In addition, a digital-to-analog converter (DAC) 18 in the residue stage generates a corresponding analog signal that represents the quantizer output, and supplies this analog signal to a summer 22. At substantially the same time as the quantizer samples the analog input signal in response to a clock signal applied at 24, a sample-and-hold (S/H) circuit 16 acquires and holds a sample of the input signal and supplies that held value to the summer 22. Summer 22 forms a difference signal representing the difference between the sampled input signal from the S/H circuit and the approximated input signal reproduction at the output of DAC 18. The resulting difference, or error signal at 28 is preferably amplified by an amplifier 30 to scale the output residue signal at 32 to take advantage of the dynamic range of the next stage in the pipeline.

The accuracy of the residue generation (and thus, the whole converter) is highly dependent on the S/H circuit and the quantizer sampling the input signal at the same time. If there is too large a difference in the timing of those samplings, then the residue signal ceases to represent the difference between the input signal at an instant and also the ability of the quantizer and DAC to reproduce that input signal value. Hence, the next stage is always presented with an error signal beyond its range of ability to correct for the conversion inaccuracy.

Due to the limitation of the performance in sampling high-frequency input signals, most converters, including the pipeline ADC, make use of a front-end S/H circuit as shown in FIG. 3. There, a S/H circuit 34 has been added between the input signal and the node 12. S/H circuit 34 is clocked at half a clock cycle from the S/H circuit 26 and the quantizer 14. With this arrangement, the input to the node 12 is not moving when it is sampled, such that there is no risk that the quantizer and residue stage would sample different values of the input waveform. In many implementations of the S/H circuit, a passive switched-capacitor sampling is usually adopted. A S/H circuit normally adds noise to the signal input as well as consumes power. To account for the higher noise floor because of the noise injection due to the sample and hold, the capacitors of the ADC stages commonly have to be increased in size to reduce the thermal noise from these stages. This essentially leads to a large increase in the power consumption of the overall ADC.

Referring now to FIG. 4, there is illustrated the ADC design disclosed by Singer and Mehr U.S. Pat. No. 6,396,429 without an explicit S/H at the front of the stage of a pipeline ADC. The operational amplifier (op-amp) and the switching network comprising the residue generator 66 is shown on top of one out of eight flash comparators 76-1, the other comparators being similarly configured and connected for a 3 bit/stage resolution.

During the tracking phase when lp is asserted, switches 92, 96, 98, 102 and 104 are closed and as signal 2 is de-asserted, switches 94 and 106 are open; switch 108 is a single-pole, double throw switch thrown to the ground position when 2 is asserted and to a reference voltage Vthl. At the inverting input node to the op-amp 1 16, there are connected for one terminal each of switch 102, input sampling capacitor Cin, feedback capacitor Cf and reference capacitors Crl through Cr8. Each of the reference capacitors, such as capacitor Crl, has another terminal connected to the pole of a single-pole, for the triple throw switch 112; one throw is connected to a positive reference voltage Vref+, one throw is connected to a negative reference voltage Vref-, and one throw is connected to a common mode voltage Vcml. When ol is asserted, switch 112 is thrown to its middle position, connecting to Vcml; when 2 is asserted and the output Dl to the first comparator 76-1 is high, switch 112 is thrown to the Vref+ position; when 02 is asserted and the output Dl to the first comparator 76-1 is low, switch 1 12 is thrown to the Vref- position. In the tracking phase, both capacitors Cin and each of Cinfl through Cinf8 are charged and track the input voltage. The sampling operation of the DAC occurs when the switch 102 opens in the falling edge of 0lp. The sample is taken relative to the common mode voltage Vcml . The sampling operation inside the flash comparators occurs on the same falling edge of 0lp when the switch 104 opens.

Separate reference capacitors (Cri in the DAC and Crfi in the flash converter, where i is an index variable) are required to accommodate the input common mode range. The reference voltages for the comparators are sampled on the falling edge of 0I as well. At this moment the input voltage Vin is sampled and is available on capacitors Cinfi, while corresponding reference voltages Vthi are sampled and are available on Crfi. After the rising edge of 02, the difference Vin - Vthi is sensed at the summing junction at the inverting inputs of the comparators. Meanwhile, the DAC transitions to the amplification phase (while 2 is asserted) although the decision from the flash is not available yet. After a short delay Tdeiay from the rising edge of the o2 signal, which is necessary to allow the difference between the input and references to be amplified inside the comparators, the latching signal Lat occurs and the comparator decision outputs Dl - D8 become available to the DAC (after the latch 1 14 regenerates).

FIG. 5 shows the flash comparators that are used in the sub-ADC block of the prior art. They consists of a pre-amplifier followed by a latch circuit. The preamplifier consists of a n-type metal-oxide-semiconductor field effect transistors (NMOS) differential pair Ml 210, M2 220 driving a p-type metal-oxide-semiconductor field effect transistors (PMOS) diode-connected load M3 230, M4 240. The impedance of this preamplifier in closed loop operation is taken into account when matching the sampling network of the comparator to the one for the residue generator. Its output is applied to the latch M9 350 - M12 380, which generates the complementary metal-oxide-semiconductor (CMOS) levels and drive the switches inside the residue generator of FIG. 5.

In contrast to the prior art, this invention preferably uses a dynamic comparator 30, which does not include a pre-amplifier as depicted in FIG. 6. The first transistors Ml - M4 210-240 are preferably biased in the linear region to adjust the threshold resistively whilst the second transistors M5 - M12 310-380 preferably form a latch. Using such a comparator, there is no need for a separate input threshold voltage for comparison. The first transistors Ml - M4 210-240 that are preferably connected to the input and reference voltages are preferably operating in the triode region and preferably act like voltage controlled resistors. By dimensioning the widths of these transistors while keeping their length constant, the threshold of the comparator 30 is preferably able to be set at the desired level. Using this comparator 30 design essentially simplifies the sub-ADC architecture and reduces the power consumption; as such design dissipates power only during the latched state.

By just inserting the dynamic comparator in FIG. 6 into the prior art topology would result in the architecture shown in FIG. 7. FIG. 8 shows the unbalanced sampling at the front end of the ADC due to timing mismatch between the comparator block 10 and the MDAC block 20. During sampling phase 0l, the MDAC 20 captures analog input V2 via the sampling capacitors 80 & 82 at the falling edge of 0lp whilst the dynamic comparator 30 makes a bit decision with VI by enabling the LATCH signal. Therefore VI becomes earlier than V2 that causes a sampled voltage difference VE known as aperture error and shows itself as an offset error at the comparator 30 outputs. This invention 100 preferably uses the topology as shown in FIG. 9, where the MDAC 20 and dynamic comparators 30 each preferably have their own sampling switches driven by the same clock. This results in no kickback noise coupled from the latch (of dynamic comparator 30) to the MDAC 20 since the comparator 30 is de-coupled from the MDAC 20 when the both switches 50 & 60 are preferably off. Also the MDAC stage no longer needs reference sampling capacitors, which essentially yields larger feedback factor than in the prior art case, and further reduces power.

Referring now to FIG. 9, the present invention relates to an analog to digital converter (ADC) 100. The ADC 100 is preferably comprised of a quantizer component 10 for sampling an incoming analog signal and generating a digital signal, and a residue generator component 20 for sampling the incoming analog signal and for generating a residual analog signal with respect to the digital signal.

Still referring to FIG. 9, it is preferred that the quantizer component 10 is switchably connected to a source 1 10 of incoming analog signals. The quantizer component 10 is preferably comprised of a comparator circuit 30. The comparator circuit 30 is preferably comprised of a plurality of first transistors (not shown) for substantially acting as voltage controlled resistors therein, and a plurality of second transistors (not shown) for substantially forming a latch therein. The comparator circuit 30 is preferably of a dynamic type wherein no pre-amplifier is preferably used therein.

It is also preferred that the residue generator 20 is switchably connected to the source 1 10 of the incoming analog signals. The input of the residue generator component is preferably connected to the output of the quantizer component. The comparator circuit 30 and the switchable connection are essentially adapted to match the sampling characteristics of the quantizer and the residue generator components 10 & 20.

The ADC is preferably further comprised of at least one switch. A first sampling switch 50 is preferably connected to after the source 110 of the incoming analog signal and to before the residue generator component 20. In addition, a second sampling switch 60 is preferably connected to after the source 1 10 of the incoming analog signal and to before the quantizer component 10. The residue generator component 20 is preferably comprised of an amplifier 40, and at least one capacitor. There is preferably provided at least one input capacitor adapted for sampling the incoming analog signal in the residue generator component 20. At least one feedback capacitor (not shown) is also preferably provided in the residue generator component 20. The residue generator component 20 is preferably further comprised of at least one third switch 70. The third switch 70 is preferably connected to a connection point located at in between the negative terminal of the amplifier 40 and the input capacitor.

There are preferably two input capacitors. The input capacitors are connected in a parallel manner to each other, the first and the second sampling capacitors 80 & 82 are switchably coupled to the source 110 of the incoming analog signal for sampling the incoming analog signal during a sampling phase, and the first and the second sampling capacitors 80 & 82 are connected to the negative input terminal of the amplifier 40. It is preferred that a feedback capacitor (not shown) is switchably connected to the source 1 10 of the incoming analog signal. The feedback capacitor is essentially adapted for sampling the incoming analog signal during the sampling phase. It is preferred that the feedback capacitor is switchably connected to the amplifier 40 output during the amplification phase. There is preferably further provided a fourth switch (not shown) that is connected to after the source 1 10 of the incoming analog signal and to before the feedback capacitor.

Preferably, the first and the second transistors 210-240 & 310-380 are arranged in such a predetermined topology for matching the sampling characteristics of the quantizer and the residue generator components 10 & 20; for enabling the first transistor 210-240 to substantially act as the voltage controlled resistors; and for enabling the second transistors 310-380 to substantially forming the latch thereat. It is also preferred that the topology 600 of the comparator circuit 30 is defined substantially as shown in FIG. 6. The terminals thereof designated as Vi _atc h are the latch voltage terminals (410), the terminals designated as V ⁺ j„ and V ^' in are the positive and the negative input voltage terminals (420a & 420b), the terminals designated as V ⁺ _out and V ^" _ou t are the positive and the negative output voltage terminals (430a & 430b), and the terminals designated as V^-ef and V ^" _re f are the positive and the negative reference voltage terminals (440a & 440b) that are connected to a reference voltage respectively. It is also preferred that the quantizer component 10 is further comprised of a quantizer sampling capacitor 90 connected to after the second sampling switch 60 and to before the comparator circuit 30. A fifth switch 120 is preferably connected to after a ground and to before a connection point 130. The connection point 130 is preferably located at in between the quantizer sampling capacitor 90 and the comparator circuit 30. With respect to the comparator circuit 30, the latch 510 formed by the second transistors 310-380 is preferably connected to the ground, as shown in FIG. 9. Lastly, the comparator circuit 30 is also preferably connected to before a digital signal output designated as D _out .

It is also preferred that the topology of the ADC 100 circuit is defined substantially as shown in FIG. 9. It is further preferred that the first and second sampling switches 50 & 60 are switched on during a first sampling phase ol and the third and the fifth switches 70 & 120 are switched on during a second sampling phase o lp. It is also preferred that the transistors Ml to M12 each of field-effect transistor. It is preferred that the present invention 100 is adapted for a 1.5bit/stage topology to be used as the first stage of the pipeline.

While in the foregoing specification this invention has been described in relation to certain preferred embodiments thereof and many details have been set forth for purpose of illustration, it will be apparent to those skilled in the art that the invention is susceptible to additional embodiments and that certain of the details described herein can be varied considerably without departing from the basic principles of the invention.