ANNEALED WAFER AND ANNEALED WAFER MANUFACTURING METHOD

Title:

ANNEALED WAFER AND ANNEALED WAFER MANUFACTURING METHOD

Document Type and Number:

WIPO Patent Application WO/2004/034457

Kind Code:

A1

Abstract:

An annealed wafer having an excellent oxide film dielectric strength characteristic of the wafer surface to serve as a device fabricating region, having a high density of oxygen precipitate in the bulk layer before the wafer is put into the device process, and having an excellent IG capability, and an annealed wafer manufacturing method are disclosed. The annealed wafer is manufactured by heat-treating a silicon wafer formed of a single crystal grown by the Czochralski method. The percentage defective of the oxide film dielectric strength in the region extending from the surface of the wafer to a depth of 5 μm is 95% or more. The density of oxygen precipitate of size having a gettering capability measured in the wafer is 1×10⁹/cm³ or more at the stage before the wafer is put into the device process.

Inventors:

TAKENO HIROSHI (JP)
SAKURADA MASAHIRO (JP)
KOBAYASHI TAKESHI (JP)

Application Number:

PCT/JP2003/012396

Publication Date:

April 22, 2004

Filing Date:

September 29, 2003

Export Citation:

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Assignee:

SHINETSU HANDOTAI KK (JP)
TAKENO HIROSHI (JP)
SAKURADA MASAHIRO (JP)
KOBAYASHI TAKESHI (JP)

International Classes:

C30B29/06; C30B33/00; C30B33/02; H01L21/322; (IPC1-7): H01L21/322; C30B29/06

Foreign References:

JP2002201093A	2002-07-16
JP2002134517A	2002-05-10
EP0502471A2	1992-09-09
EP0090320A1	1983-10-05
EP1035234A1	2000-09-13
EP0890662A1	1999-01-13

Other References: